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| ds07-16602-1e fujitsu semiconductor data sheet copyright?2007 fujitsu li mited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 32-bit microcontroller cmos fr60 mb91460 series mb91461 description mb91461 is a line of the general- purpose 32-bit risc microcontrollers designed for embedded control applica- tions such as consumer devices and vehicle system, which require high-speed real-time processing. mb91461 uses the fr60 cpu compatible with the fr family* cpus. mb91461 contains the lin-uart and can controller. * : fr, the abbreviation of fujitsu risc contro ller, is a line of products of fujitsu limited. features ? fr60 cpu 32-bit risc, load/store architecture, five-stage pipeline maximum operating frequency : 80 mhz (oscillation fr equency 20 mhz, oscillation frequency 4 multiplier (pll clock multiplication method)) 16-bit fixed-length instructions (basic instructions) instruction execution speed : 1 instruction per cycle instructions including memory-to-memory transfer, bit manipulation instructions, and barrel shift instructions: instructions suitable for embedded applications function entry/exit instructions and register data mu lti load store instructions: instructions supporting c language register interlock function : facilitating assembly-language coding built-in multiplier with instruction-level support signed 32-bit multiplication : 5 cycles signed 16-bit multiplication : 3 cycles interrupt (pc/ps saving) : 6 cycles (16 priority levels) (continued)
mb91460 series 2 harvard architecture enabling simultaneous ex ecution of both program access and data access instructions compatible with the fr family ? internal peripheral resources mb91461 does not contain the rom and flash memory. internal ram capacity : instruction cache 4 kb ytes + 64 kbytes (instruction/data common ram) general-purpose port : maximum 72 ports dmac (dma controller) maximum of 5 channels for simultaneous operation is possible. (1 channel for external-to-external) 3 transfer sources (external pin/internal peripheral/software) activation source can be selected using software. addressing mode with 32-bit full address indication (increment/decrement/fixed) transfer mode (demand transfer/burst transfer/step transfer/block transfer) fly-by transfer support (between external i/o and memory) transfer data size selection 8/16/32-bit multi-byte transfer enabled (by software) dmac descriptor in i/o areas (200 h to 240 h , 1000 h to 1024 h ) a/d converter (sequential comparison) 10-bit resolution: 13 channels conversion time: 1 s (peripheral macro operation clock at 16.67 mhz) external interrupt input: 16 channels pins shared with rx pins of can0 and can1 bit search module (for realos) function of searching for the first ?0? data/ ?1? data/ change bit position in 1 word from the msb (upper bit) lin-uart (full duplex double buffer): 7 channels clock synchronous/asynchronous selectable sync-break detection internal dedicated baud rate generator i 2 c* bus interface (400 kbps supported): 3 channels master/slave sending and receiving arbitration function, clock synchronization function can controller (c-can) : 2 channels maximum transfer speed : 1 mbps 32 sent/received message buffers 16-bit ppg timer : 8 channels 16-bit reload timer : 5 channels 16-bit free-run timer : 4 channels (1 channel each for icu and ocu) input capture : 4 channels (work with free-run timer) output compare : 4 channels (work with free-run timer) watchdog timer watchdog reset output pin available real-time clock low-power consumption mode: sl eep/stop/shutdown mode function (continued) mb91460 series 3 (continued) ? package : lqfp-176 (fpt-176p-m07) ? cmos 0.18 m technology ? 3 v/5 v power supplies [internal logic is kept at 1.8 v by step-down circuit, some i/os have the withstand voltage of 5.0 v] ? operating temperature range : between ? 40c and + 85c * : purchase of fujitsu i 2 c components conveys a lic ense under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips. mb91460 series 4 pin assignment note : (1) to (3) are 3.3 v/5 v pin supported pin, and c an set 3.3 v and 5 v to the voltage in each block. i 2 c pin in (1) can be inputted at 5 v power supply. however, 3.3 v of the input threshold value is used as the standard value regardless of the power supply voltage. if 5 v is set in (1) or (2), also set 5 v to (3). 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 18 19 20 21 22 2 3 24 25 26 27 28 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 3 8 3 9 40 41 42 4 3 44 vss p24_2/int2 p24_ 3 /int 3 p22_6/sda1/int15 p22_7/scl1 p24_4/sda2/int4 p24_5/scl2/int5 dreq0 dack0 deop0 vcc 3 vcc 3 vss c_1 cs4 cs 3 cs2 cs1 cs0 iord iowr rdy brq bgrnt rd wr0 wr1 sysclk as vcc 3 c_2 vss x0 x1 vss d16 d17 d18 d19 d20 d21 d22 d2 3 vcc 3 176 175 174 17 3 172 171 170 169 168 167 166 165 164 16 3 162 161 160 159 158 157 156 155 154 15 3 152 151 150 149 148 147 146 145 144 14 3 142 141 140 1 3 9 1 3 8 1 3 7 1 3 6 1 3 5 1 3 4 1 33 vcc5 p17_ 3 /ppg 3 p17_2/ppg2 p17_1/ppg1 p17_0/ppg0 p14_ 3 /icu 3 /tin 3 /trg 3 p14_2/icu2/tin2/trg2 p14_1/icu1/tin1/trg1 p14_0/icu0/tin0/trg0 p22_ 3 p22_2/int1 3 p22_0/int12 p2 3 _6/int11 p2 3 _4/int10 vcc5 vss p15_ 3 /ocu 3 /tot 3 p15_2/ocu2/tot2 p15_1/ocu1/tot1 p15_0/ocu0/tot0 p18_2/sck6 p18_1/sot6 p18_0/sin6 p19_6/sck5 p19_5/sot5 p19_4/sin5 p19_2/sck4 p19_1/sot4 p19_0/sin4 vcc5 vss p20_6/sck 3 /frck 3 p20_5/sot 3 p20_4/sin 3 p20_2/sck2/frck2 p20_1/sot2 p20_0/sin2 p21_6/sck1/frck1 p21_5/sot1 p21_4/sin1 p21_2/sck0/frck0 p21_1/sot0 p21_0/sin0 vcc5 1 3 2 1 3 1 1 3 0 129 128 127 126 125 124 12 3 122 121 120 119 118 117 116 115 114 11 3 112 111 110 109 108 107 106 105 104 10 3 102 101 100 99 98 97 96 95 94 9 3 92 91 90 89 vss init trst md0 md1 md2 md 3 p2 3 _ 3 /tx1 p2 3 _2/rx1/int9 p2 3 _1/tx0 p2 3 _0/rx0/int8 p24_7/int7 p24_6/int6 p22_5/scl0 p22_4/sda0/int14 p24_1/int1 p24_0/int0 avrh avcc 3 avss/avrl p28_4/an12 p28_ 3 /an11 p28_2/an10 p28_1/an9 p28_0/an8 p29_7/an7 p29_6/an6 p29_5/an5 p29_4/an4 p29_ 3 /an 3 p29_2/an2 p29_1/an1 p29_0/an0 wdreset break iclk ics2 ics1 ics0 icd 3 icd2 icd1 icd0 vcc 3 45 46 47 48 49 50 51 52 5 3 54 55 56 57 58 59 60 61 62 6 3 64 65 66 67 68 69 70 71 72 7 3 74 75 76 77 78 79 80 81 82 8 3 84 85 86 87 88 vss d24 d25 d26 d27 d28 d29 d 3 0 d 3 1 a00 a01 a02 vcc 3 vss a0 3 a04 a05 a06 a07 a08 a09 a10 a11 a12 a1 3 a14 a15 a16 vcc 3 vss a17 a18 a19 a20 a21 a22 a2 3 nmi p16_7/atg p17_4/ppg4 p17_5/ppg5 p17_6/ppg6 p17_7/ppg7 vss (1) ( 3 ) (2) (fpt-176p-m07) (top view) mb91460 series 5 pin description (continued) pin no. pin name i/o i/o circuit type* function 2 p24_2 i/o d general-purpose input/output port int2 external interrupt input pin 3 p24_3 i/o d general-purpose input/output port int3 external interrupt input pin 4 p22_6 i/o open drain c general-purpose input/output port sda1 i 2 c bus data input/output pin int15 external interrupt input pin 5 p22_7 i/o open drain c general-purpose input/output port scl1 i 2 c bus clock input/output pin 6 p24_4 i/o open drain c general-purpose input/output port sda2 i 2 c bus data input/output pin int4 external interrupt input pin 7 p24_5 i/o open drain c general-purpose input/output port scl2 i 2 c bus clock input/output pin int5 external interrupt input pin 8 dreq0 i h dma external transfer request input 9 dack0 o h dma external transfer acknowledge output 10 deop0 o h dma external transfer eop (end of process) output 15 cs4 o h chip select 4 output 16 cs3 o h chip select 3 output 17 cs2 o h chip select 2 output 18 cs1 o h chip select 1 output 19 cs0 o h chip select 0 output 20 iord o h read strobe output at dma fly-by transfer 21 iowr o h write strobe output at dma fly-by transfer 22 rdy i h external ready input 23 brq i h external bus open request input 24 bgrnt o h external bus open acknowledge output 25 rd o h external read strobe output 26 wr0 o h external write strobe output 27 wr1 o h external write strobe output 28 sysclk o h system clock output 29 as o h address strobe output 33 x0 ? g clock (oscillation) input 34 x1 ? g clock (oscillation) output mb91460 series 6 (continued) pin no. pin name i/o i/o circuit type* function 36 to 43 46 to 53 d16 to d31 i/o h external data bus signal 54 to 56 59 to 72 75 to 81 a00 to a23 o h external address bus signal 82 nmi i h nmi (non maskable interrupt) input 83 p16_7 i/o h general-purpose input/output port atg a/d converter external trigger input 84 to 87 p17_4 to p17_7 i/o h general-purpose input/output ports ppg4 to ppg7 ppg timer output pins 90 to 93 icd0 to icd3 i/o h data inpu t/output pins for development tool 94 to 96 ics0 to ics2 o h status output pins for development tool 97 iclk o i clock output pin for development tool 98 break i h break input pin for development tool 99 wdreset o j watchdog reset output pin 100 to 107 p29_0 to p29_7 i/o f general-purpose input/output ports an0 to an7 analog input pins for a/d converter 108 to 112 p28_0 to p28_4 i/o f general-purpose input/output ports an8 to an12 analog input pins for a/d converter 116, 117 p24_0, p24_1 i/o d general-purpose input/output ports int0, int1 external interrupt input pins. can be used as a return source from shutdown. 118 p22_4 i/o open drain c general-purpose input/output port sda0 i 2 c bus data input/output pin int14 external interrupt input pin 119 p22_5 i/o open drain c general-purpose input/output port scl0 i 2 c bus clock input/output pin 120 p24_6 i/o d general-purpose input/output port int6 external interrupt input pin. can be used as a return source from shutdown. 121 p24_7 i/o d general-purpose input/output port int7 external interrupt input pin. can be used as a return source from shutdown. mb91460 series 7 (continued) pin no. pin name i/o i/o circuit type* function 122 p23_0 i/o d general-purpose input/output port rx0 rx input pin of can0 int8 external interrupt input pin. can be used as a return source from shutdown. 123 p23_1 i/o d general-purpose input/output port tx0 tx output pin of can0 124 p23_2 i/o d general-purpose input/output port rx1 rx input pin of can1 int9 external interrupt input pin. can be used as a return source from shutdown. 125 p23_3 i/o d general-purpose input/output port tx1 tx output pin of can1 126 md3 i a mode setting pins 127 md2 i a 128 md1 i a 129 md0 i b 130 trst i e reset input pin for development tool 131 init i b external reset input 134 p21_0 i/o d general-purpose input/output port sin0 data input pin of uart0 135 p21_1 i/o d general-purpose input/output port sot0 data output pin of uart0 136 p21_2 i/o d general-purpose input/output port sck0 clock input/output pin of uart0 frck0 external clock input pin of free-run timer0 137 p21_4 i/o d general-purpose input/output port sin1 data input pin of uart1 138 p21_5 i/o d general-purpose input/output port sot1 data output pin of uart1 139 p21_6 i/o d general-purpose input/output port sck1 clock input/output pin of uart1 frck1 external clock input pin of free-run timer1 140 p20_0 i/o d general-purpose input/output port sin2 data input pin of uart2 mb91460 series 8 (continued) pin no. pin name i/o i/o circuit type* function 141 p20_1 i/o d general-purpose input/output port sot2 data output pin of uart2 142 p20_2 i/o d general-purpose input/output port sck2 clock input/output pin of uart2 frck2 external clock input pin of free-run timer2 143 p20_4 i/o d general-purpose input/output port sin3 data input pin of uart3 144 p20_5 i/o d general-purpose input/output port sot3 data output pin of uart3 145 p20_6 i/o d general-purpose input/output port sck3 clock input/output pin of uart3 frck3 external clock input pin of free-run timer3 148 p19_0 i/o d general-purpose input/output port sin4 data input pin of uart4 149 p19_1 i/o d general-purpose input/output port sot4 data output pin of uart4 150 p19_2 i/o d general-purpose input/output port sck4 clock input/output pin of uart4 151 p19_4 i/o d general-purpose input/output port sin5 data input pin of uart5 152 p19_5 i/o d general-purpose input/output port sot5 data output pin of uart5 153 p19_6 i/o d general-purpose input/output port sck5 clock input/output pin of uart5 154 p18_0 i/o d general-purpose input/output port sin6 data input pin of uart6 155 p18_1 i/o d general-purpose input/output port sot6 data output pin of uart6 156 p18_2 i/o d general-purpose input/output port sck6 clock input/output pin of uart6 157 to 160 p15_0 to p15_3 i/o d general-purpose input/output ports ocu0 to ocu3 output compare output pins tot0 to tot3 reload timer output pins 163 p23_4 i/o d general-purpose input/output port int10 external interrupt input pin mb91460 series 9 (continued) *: for details of i/o circuit types, refer to ? i/o circuit type?. pin no. pin name i/o i/o circuit type* function 164 p23_6 i/o d general-purpose input/output port int11 external interrupt input pin 165 p22_0 i/o d general-purpose input/output port int12 external interrupt input pin 166 p22_2 i/o d general-purpose input/output port int13 external interrupt input pin 167 p22_3 i/o d general-purpose input/output port 168 to 171 p14_0 to p14_3 i/o d general-purpose input/output ports icu0 to icu3 input capture input pins tin0 to tin3 external trigger input pins of reload timer trg0 to trg3 external trigger input pins of ppg 172 to 175 p17_0 to p17_3 i/o d general-purpose input/output ports ppg0 to ppg3 ppg timer output pins mb91460 series 10 [power supply/gnd pins] pin number pin name i/o function 1, 13, 32, 35, 45, 58, 74, 88, 132, 146, 161 vss (vss) gnd pins 11, 12, 30, 44, 57, 73, 89 vcc3 (vcc3) 3.3 v power supply pins 133, 147 vcc5 (vcc5) 5 v power supply pins. these pins are i/o power supplies corresponding to 116 to 145 pi ns. the corresponding i/o pin operates at 3.3 v when supply ing 3.3 v, and at 5 v when supplying 5v. be sure to suppl y 5 v if more than one 5v operating pin is specified, or 5v is supplied at pin 162 or pin 176. 162 vcc5 (vcc5) 5 v power supply pin. this pin is an i/o power supply corresponding to 148 to 160 pi ns. the corresponding i/o pin operates at 3.3 v when supply ing 3.3 v, and at 5v when supplying 5 v. be sure to supply 5 v if more than one 5 v operating pin is specified. 176 vcc5 (vcc5) 5 v power supply pin. this pin is an i/o power supply corresponding to 2 to 7 pi ns. the corresponding i/o pin operates at 3.3 v when supply ing 3.3 v, and at 5 v when supplying 5 v. be sure to supply 5 v if more than one 5 v operating pin is specified. 113 avss/avrl (avss) analog gnd pin for a/d converter 114 avcc3 (avcc3) 3.3 v power supply pin for a/d converter 115 avrh (avrh) reference power supply pin for a/d converter 14 c_1 ? capacitor connection pin for internal regulator. connect a 4.8 f capacitor. 31 c_2 ? capacitor connection pin for internal regulator. connect a 4.8 f capacitor. mb91460 series 11 i/o circuit type (continued) type circuit type remarks a 5 v cmos hysteresis input b 5 v cmos hysteresis input c input/output pin for i 2 c i ol = 3 ma with stand voltage of 5 v with standby control n-ch input 5 v level p-ch input 5 v level n-ch output drive n-ch input standby control mb91460 series 12 (continued) type circuit type remarks d 5 v cmos output i ol = 4 ma 5 v cmos input 5 v cmos hysteresis input with 50 k ? pull-up/pull-down control with standby control e 3.3 v cmos hysteresis input with stand voltage of 5 v with standby control f 3.3 v cmos output i ol = 4 ma 3.3 v cmos input 3.3 v cmos hysteresis input analog input with standby control n-ch p-ch p-ch n-ch pull-down control output drive n-ch output drive p-ch standby control standby control input input 5 v level pull-up control input 3.3 v level n-ch p-ch 3.3 v level analog input output drive n-ch output drive p-ch standby control standby control input input mb91460 series 13 (continued) type circuit type remarks g 3.3 v oscillation cell h 3.3 v cmos output i ol = 4 ma 3.3 v cmos input 3.3 v cmos hysteresis input with 33 k ? pull-up/pull-down control with standby control i, j 3.3 v cmos output i : i ol = 8 ma j : i ol = 4 ma standby control input 3.3 v level n-ch p-ch n-ch p-ch pull-up control output drive n-ch input standby control output drive p-ch pull-down control input standby control 3.3 v level n-ch p-ch output drive p-ch output drive n-ch 3.3 v level mb91460 series 14 handling devices ? preventing latch-up latch-up may occur in a cmos ic if a voltage higher than v cc or less than v ss is applied to an input or output pin or if a voltage exceeding the rating is applied betw een vcc pin and vss pin. if latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. therefore, when using a cmos ic, do not exceed the maximum rating. ? handling of unused input pins if unused input pins are left open, abnormal operation may result. any unus ed input pins should be connected to pull-up or pull-down resistor. ? power supply pins when provided with multiple vcc pins or vss pins, the device is designed such that the pins having equal potential are interconnected internally to prevent malfunctions such as latch-up. all of these pins must however be connected to the power supply and ground externally to reduce unwanted radiation, to prevent the strobe signal from malfunctioning due to a rise of ground level, and to follow the total output current standards. in addition, vcc pin and vss pin of this device should be connected from the power supply source with the lowest possible impedance. it is also recommended to connect a ceramic capacitor of approximately 0.1 f as a bypass capacitor between vcc pin and vss pin near this device. this series has a built-in step-down regul ator. connect a bypass capacitor of 4.7 f to c_1 and c_2 pins for the regulator. ? crystal oscillator circuit noise in proximity to the x0 and x1 pins can cause abnormal operation in this device. printed circuit boards should be designed so that the x0 and x1 pins, and crys tal oscillator, as well as bypass capacitors connected to ground, are placed as cl ose together as possible. the use of printed circuit board architecture in which the x0 and x1 pins are surrounded by ground contributes to stable operation and is strongly recommended. please ask the crystal maker to evaluate the oscillatio nal characteristics of the crystal and this device. ? notes on using external clock in principle, when using external clock, supply a clock to the x0 pin and x1 pin simultaneously. also, an opposite phase clock to the x0 pin must be supp lied to the x1 pin. however, in this case the stop mode (oscillation stop mode) must not be used (this is because the x1 pin stops at ?h? output in stop mode). example of using external clock (normal) x0 x1 (note) stop mode (oscillation stop mode) cannot be used. mb91460 series 15 ? mode pins (md0 to md3) when using mode pins, connect them directly to vcc pin or vss pin. to prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and vcc pin or vss pin on the printed circuit board as possible and connect them with low impedance. ? power-on sequences for 3.3 v and 5 v immediately after power-on, keep ?l? level input to the init pin for the oscillation stabilization wait time (8 ms) to ensure the oscillation stabilization wa it time for the oscillator circuit. there is no power-on sequences. when executing a reset cancellation (changing init pin from ?l? level to ?h? level) , be sure to execute it while 3 v and 5 v power supplies are stable. ? caution on operations during pll clock mode on this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the pll clock mode is selected, a self-oscillator circuit contained in the pll may c ontinue its operation at its self-running frequency. however, fujitsu will not guaran tee results of operations if such failure occurs. ? external bus setting this model guarantees the maximum frequency of 40 mhz for the external bus clock sysclk. setting the base clock frequency to 80 mhz without changing the initial val ue of divr1 (external bus base clock division setting register) sets the external bus freque ncy also to 80 mhz. before changing the base clock frequency, set sysclk no t exceeding 40 mhz. ? pull-up control connecting a pull-up resistor to the pin serving as an external bus pin cannot guarantee the ac standard. ? notes on ps register since some instructions process the ps register in adv ance, the following exceptional operations may cause a break in the interrupt process routine or an update of di splay contents of the flag in the ps register when the debugger is being used. in either case, as the devi ce is designed to carry out reprocessing correctly upon returning from such an eit event, it performs o perations before and afte r the eit as specified. 1) the following operations may be performed when the instruction immediately followed by a div0u/div0s instruction accepts a user interrupt/nmi, executes a step , or breaks in response to a data event or emulator menu. -d0 and d1 flags are updated in advance. -an eit process routine (user interrupt/nmi or emulator) is executed. -upon returning from the eit, the div0u/div0s instru ction is executed and the d0 and d1 flags are updated to the same values as those in 1). 2) the following operations are performed when each instruction of or ccr, st ilm, mov ri and ps is executed to enable interrupts while a user interrupt/nmi source has been occurring. -the ps register is updated in advance. -an eit process routine (user interrupt/nmi or emulator) is executed. -upon returning from the eit, the above instructions are executed and the ps register is updated to the same value as that in 1). mb91460 series 16 notes on debugger ? step execution of reti instruction in the environment where interrupts occur frequentl y when stepping, only the corresponding interrupt process routines are executed repeatedly. as the result of that, the main routine and low-interrupt-level programs are not executed (for example, if an interrupt to the time base timer is enabled, a break always occurs at the beginning of the time base routine when stepping reti) . disable the corresponding interrupts when the debug on the corresponding interrupt process routines becomes unnecessary. ? break function if the target address of a hardware break (including an event break) is set to the address currently contained in the system stack pointer or in the ar ea containing the stack pointer, t he user program causes a break after execution of one instruction even though there is no actual data access instruction in the user program. to prevent this, do not set (word) access to the area co ntaining the address of the system stack pointer as the target of a hardware break (including an event break). ? operand break if a stack pointer exists in the area which is set as the dsu operand break, malfunctions may occur. do not set the access to the areas containing the address of sy stem stack pointer as a target of data event break. mb91460 series 17 dsu4 (ice) dedicated connection pins mb91461 dsu4 (ice) dedicated connection pins ? user target side connec tor and the mb91461 connection the recommended connector for the us er target side is shown below. manufacturer : yamaichi electronics co., ltd. model number : fap-20-08#* note : the asterisk (*) in the model number represents each of the following pin shapes: ? 1 : right angle/wrapping ? 2 : right angle/solder dip ? 4 : straight/solder dip pin no. pin name function 93 to 90 icd3 to icd0 data input/output pins for development tool 96 to 94 ics2 to ics0 status output pins for development tool 97 iclk clock pin for development tool 98 break break pin for development tool 130 trst reset pin for development tool (3 v/5 v supported input pin) pin 19 pin 20 pin 1 pin 2 mb91460 series 18 connector pin no. signal line name i/o pin handling 1 evcc2 i open 2 evcc3 i open 3dsuio i/oopen 4uvcc ouser v cc output 6 xrstin o connected to user circuit init signal 8 plvl i open 5xtrst i mb91461 connected to trst (130 pin) 7 xinit i connected to init (131 pin) 9gnd ? connected to vss 10 break i connected to break (98 pin) 11 icd3 i/o connected to icd3 (93 pin) 12 icd2 connected to icd2 (92 pin) 13 icd1 connected to icd1 (91 pin) 14 icd0 connected to icd0 (90 pin) 15 gnd ? connected to vss 16 ics2 o connected to ics2 (96 pin) 17 ics1 connected to ics1 (95 pin) 18 ics0 connected to ics0 (94 pin) 19 gnd ? connected to vss 20 iclk o connected to iclk (97 pin) mb91460 series 19 handling of dedicated pin for dsu4 (ice) in mass production handling of dedicated pin for dsu4 (ice) in mass production connection handling of the reset pin (trst ) for development tool (dsu) in mass production since the reset pin (trst ) for development tool is the input pin sup porting 3v/5v, it c an be connected to init pin directly. mb91461 pin no. pin name pin handling 93 to 90 icd3 to icd0 open 96 to 94 ics2 to ics0 open 97 iclk open 98 break open 130 trst connected to init (131 pin: external reset input pin) reset input init tr s t mb91461 mb91460 series 20 block diagram tr s t break ic s 0 to ic s 2 icd0 to icd 3 dreq0 dack0 deop0 iowr iord trg0 to trg 3 ppg0 to ppg7 tin0 to tin 3 tot0 to tot 3 frck0 to frck 3 icu0 to icu 3 ocu0 to ocu 3 s da0 to s da2 s cl0 to s cl2 an0 to an12 at g port s in0 to s in6 s ot0 to s ot6 s ck0 to s ck6 nmi int0 to int15 s y s clk a s rd wr0 wr1 brq bgrnt c s 0 to c s 4 a2 3 to a00 d 3 1 to d16 rx0,rx1 tx0,tx1 r- bus 16 i- bus 3 2 d- bus 3 2 iclk : pin for development tool ram 64 kbytes clock control 32 ? 16 bus adapter can 2 channels external bus interface bus converter dmac 5 channels bit search dsu (debug support) instruction cache 4 kbytes fr60 cpu core ppg 8 channels reload timer 5 channels free-run timer 4 channels input capture 4 channels output compare 4 channels interrupt controller external interrupt 16 channels port interface lin-uart 7 channels (including bgr) i 2 c 3 channels rtc a/d converter 13 channels mb91460 series 21 cpu and control unit the fr family cpu is a high perfor mance core that is designed based on the risc architecture with advanced instructions for embedded applications. 1. features adoption of risc architecture basic instruction: 1 instruction per cycle general-purpose registers: 32-bit 16 registers 4 gbytes linear memory space multiplier installed 32-bit 32-bit multiplication: 5 cycles 16-bit 16-bit multiplication: 3 cycles enhanced interrupt processing function quick response speed (6 cycles) multiple-interrupt support level mask function (16 levels) enhanced instructions for i/o operation memory-to-memory transfer instruction bit processing instruction basic instruction word length: 16 bits low-power consumption sleep mode/stop mode/shutdown mode mb91460 series 22 2. internal architecture the fr family cpu uses the harvard architecture in which the instruction bus and data bus are independent of each other. a 32-bit ? 16-bit bus adapter is connected to the 32-bit bus (d-bus) to provide an interface between the cpu and peripheral resources. a harvard ? princeton bus converter is connected to both t he i-bus and d-bus to provide an interface between the cpu and the bus controller. the following figure shows the internal architecture structure. r- bus 16 i- bus 3 2 d- bus 3 2 ram 64 kbytes 32 ? 16 bus adapter can 2 channels external bus interface bus converter dmac 5 channels bit search dsu (debug support) instruction cache ram fr60 cpu core peripheral resource mb91460 series 23 3. programming model basic programming model ilm scr ccr fp sp ac . . . . . . . . . . . . xxxx xxxx h 0000 0000 h xxxx xxxx h . . . . . . . . . r0 r1 r12 r13 r14 r15 pc rs rp tbr ssp usp mdl mdh . . . . . . 32 bits initial value general-purpose registers program counter program status table base register return pointer system stack pointer user stack pointer multiply and divide result registers mb91460 series 24 4. registers general-purpose register registers r0 to r15 are general-purpose registers. thes e registers can be used as accumulators for computation operations and as pointers for memory access. of the 16 registers, enhanced commands are provided for th e following registers to enable their use for particular applications. r13 : virtual accumulator r14 : frame pointer r15 : stack pointer initial values at reset are undefined for r0 to r14. the value for r15 is 00000000 h (ssp value). ? ps (program status) this register holds the program status, and is divided into three parts, ilm, scr, and ccr. all undefined bits (-) in the diagram are reserved bits. the read values are always ?0?. write access to these bits is invalid. fp sp ac . . . . . . . . . . . . xxxx xxxx h 0000 0000 h xxxx xxxx h . . . . . . . . . r0 r1 r12 r13 r14 r15 . . . . . . 32 bits initial value bit position b it 20 b it 0 b it 7 b it 8 b it 10 b it 16 ilm s cr ccr b it 3 1 mb91460 series 25 ? ccr (condition code register) s : stack flag i : interrupt enable flag n : negative enable flag z : zero flag v : overflow flag c : carry flag ? scr (system condition register) flag for step multiplication (d1, d0) this flag stores interim data during execution of step multiplication. step trace trap flag (t) this flag indicates whether the step trace trap is enabled or disabled. the step trace trap function is used by emulators. when an emulator is in us e, it cannot be used in execution of user programs. ? ilm this register stores interrupt level mask values, and the values stored in ilm4 to ilm0 are used for level masking. the register is initialized to value ?01111 b ? at reset. ? pc (program counter) the program counter indicates the address of the instruction that is being executed. the initial value at reset is undefined. - - 00xxxx b b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 c v z n i s initial value b it 10 b it 8 b it 9 d1 d0 t xx0 b initial value b it 1 8b it 16 b it 17 ilm2 ilm1 ilm0 01111 b ilm 3 ilm4 b it 20 b it 19 initial value b it 0 b it 3 1 xxxxxxxx h initial value mb91460 series 26 ? tbr (table base register) the table base register stores the starting addr ess of the vector table used in eit processing. the initial value at reset is 000ffc00 h . ? rp (return pointer) the return pointer stores the address for return from subroutines. during execution of a call instruction, the pc value is transferred to this rp register. during execution of a ret instruction, the content s of the rp register are transferred to pc. the initial value at reset is undefined. ? usp (user stack pointer) the user stack pointer, when the s flag is ?1?, this register functions as the r15 register. ? the usp register can also be explicitly specified. the initial value at reset is undefined. ? this register cannot be used with reti instructions. ? multiply & divide registers these registers are for multiplication and divi sion, and are each 32 bits in length. the initial value at reset is undefined. b it 0 b it 3 1 000ffc00 h initial value b it 0 b it 3 1 xxxxxxxx h initial value b it 0 b it 3 1 xxxxxxxx h initial value b it 0 mdl b it 3 1 mdh mb91460 series 27 mode setting in the fr family, the mode pins (md2, md1, md0) and the mode register (modr) are used to set the operating mode. 1. mode pins the three pins md2, md1, md0 are used to sp ecify the mode vector fetch related settings. settings other than shown in the table are not allowed. * : always use md3 with ?0?. note : the fr family does not support the exte rnal mode vector fetch using multiplex bus. 2. mode register (modr) the data written to the mode register us ing mode vector fetch is called mode data. after the mode register (modr) is set, the device operat es according to the operation mode set in this register. the mode register is set by all reset sources. user programs cannot write data to the mode register. rewriting is allowed in the emulator mode. in this case, use an 8-bit length data transfer instruction. a 16/32-bit length transfer instruct ion cannot be used for writing. description of the mode register is given below. [mode register description] [bit7 to bit3] reserved bits be sure to set these bits to ?00000 b ?. operation is not guaranteed when any value other than ?00000 b ? is set. [bit2] roma (internal enable bit) the roma bit is used to set whether to enable the internal f-bus ram and f-bus rom areas. note : use ?0? in mb91461. mode pins* mode name reset vector access area remarks md2 md1 md0 0 0 0 internal rom mode vector internal not allowed 0 0 1 external rom mode vector external bus width is set by mode register. roma function remarks 0 external rom mode internal f-bus ram becomes valid. the internal rom area (40000 h to fffff h ) is used as an external area. 1 internal rom mode internal f-bus ram and f-bus rom become valid. b it 5 b it 3 b it 4 000 0 0 b it 7 b it 6 b it 0 b it 2 b it 1 wth0 roma wth1 xxxxxxxx b initial value operation mode setting bits mb91460 series 28 [bit1, bit0] wth1, wth0 (bus width setting bits) these bits are used to set the bus width to be used in the external bus mode. when the operation mode is the external bus mode, thes e values are set in bits bw1 and bw0 in amd0 (cs0 area). wth1 wth0 function remarks 0 0 8-bit bus width external bus mode 0 1 16-bit bus width external bus mode 10 ? setting disabled 1 1 single chip mode setting disabled mb91460 series 29 memory space 1. memory space the fr family has 4 gbytes of logical address space (2 32 addresses) available to the cpu by linear access. direct addressing area the following address space area is used for i/o. this area is called direct addressing area, and the ad dress of an operand can be specified directly in an instruction. the size of directly addressable area depends on th e length of the data being accessed as shown below. byte data access : 000 h to 0ff h half word access : 000 h to 1ff h word data access : 000 h to 3ff h 2. memory map 0000 0000 h 0000 0400 h 0000 8 000 h 0001 0000 h 0000 bfff h 0002 0000 h 000 3 0000 h 0004 0000 h 0010 0000 h ffff ffff h i/o i/o f- bus ram bi-rom i/o : acce ss prohi b ited external rom external bus mode direct addressing area refer to ? i/o map?. external area reset/vector mode external area mb91461 instruction cache each mode is set depending on t he mode vector fetch after init is negated. (for details on mode settings, refer to ? mode setting?.) mb91460 series 30 i/o map note : initial values of register bits are represented as follows: ? 1 ? : initial value ? 1 ? ? 0 ? : initial value ? 0 ? ? x ? : initial value ? undefined ? ? - ? : no physical register at this location access is barred with an un defined data access attribute. address register block + 0 + 1 + 2 + 3 000000 h pdr0 [r/w]b xxxxxxxx pdr1 [r/w]b xxxxxxxx pdr2 [r/w]b xxxxxxxx pdr3 [r/w]b xxxxxxxx t-unit port data register read/write attribute, access unit (b: byte, h: half word, w: word) register initial value after reset register name (column 1 register at address 4n, column 2 register at address 4n + 1...) leftmost register address (for word access, the register in column 1 becomes the msb side of the data.) mb91460 series 31 (continued) address register block 0123 000000 h reserved r-bus port data register 000004 h reserved 000008 h reserved 00000c h reserved pdr14 [r/w] b,h ----xxxx pdr15 [r/w] b,h ----xxxx 000010 h pdr16 [r/w] b,h x------- pdr17 [r/w] b,h xxxxxxxx pdr18 [r/w] b,h -----xxx pdr19 [r/w] b,h -xxx-xxx 000014 h pdr20 [r/w] b,h -xxx-xxx pdr21 [r/w] b,h -xxx-xxx pdr22 [r/w] b,h xxxxxx-x pdr23 [r/w] b,h -x-xxxxx 000018 h pdr24 [r/w] b,h xxxxxxxx reserved 00001c h pdr28 [r/w] b,h ---xxxxx pdr29 [r/w] b,h xxxxxxxx reserved 000020 h reserved 000024 h to 00002c h reserved reserved 000030 h eirr0 [r/w] b 00000000 enir0 [r/w] b 00000000 elvr0 [r/w] b,h 00000000 00000000 external interrupt (int0 to int7) nmi 000034 h eirr1 [r/w] b 00000000 enir1 [r/w] b 00000000 elvr1 [r/w] b,h 00000000 00000000 external interrupt (int 8 to int15 ) 000038 h dicr [r/w] b -------0 hrcl [r/w] b 0--11111 reserved delay interrupt 00003c h reserved reserved 000040 h scr00 [r/w,w] b,h,w 00000000 smr00 [r/w,w] b,h,w 00000000 ssr00 [r/w,r] b,h,w 00001000 rdr00/tdr00 [r/w] b,h,w 00000000 uart (lin) 0 000044 h escr00 [r/w] b,h 00000x00 eccr00 [r/w,r,w] b,h -00000xx reserved 000048 h scr01 [r/w,w] b,h,w 00000000 smr01 [r/w,w] b,h,w 00000000 ssr01 [r/w,r] b,h,w 00001000 rdr01/tdr01 [r/w] b,h,w 00000000 lin-uart 1 00004c h escr01 [r/w] b,h 00000x00 eccr01 [r/w,r,w] b,h -00000xx reserved mb91460 series 32 (continued) address register block 0123 000050 h scr02 [r/w,w] b,h,w 00000000 smr02 [r/w,w] b,h,w 00000000 ssr02 [r/w,r] b,h,w 00001000 rdr02/tdr02 [r/w] b,h,w 00000000 lin-uart 2 000054 h escr02 [r/w]b,h 00000x00 eccr02 [r/w,r,w] b,h -00000xx reserved 000058 h scr03 [r/w,w] b,h,w 00000000 smr03 [r/w,w] b,h,w 00000000 ssr03 [r/w,r] b,h,w 00001000 rdr03/tdr03 [r/w] b,h,w 00000000 lin-uart 3 00005c h escr03 [r/w] b,h 00000x00 eccr03 [r/w,r,w] b,h -00000xx reserved 000060 h scr04 [r/w,w] b,h,w 00000000 smr04 [r/w,w] b,h,w 00000000 ssr04 [r/w,r] b,h,w 00001000 rdr04/tdr04 [r/w] b,h,w 00000000 lin-uart 4 000064 h escr04 [r/w] b,h,w 00000x00 eccr04 [r/w,r,w] b,h,w -00000xx fsr04 [r] b,h,w ---00000 fcr04 [r/w] b,h,w 0001-000 000068 h scr05 [r/w,w] b,h,w 00000000 smr05 [r/w,w] b,h,w 00000000 ssr05 [r/w,r] b,h,w 00001000 rdr05/tdr05 [r/w] b,h,w 00000000 lin-uart 5 00006c h escr05 [r/w] b,h,w 00000x00 eccr05 [r/w,r,w] b,h,w -00000xx fsr05 [r] b,h,w ---00000 fcr05 [r/w] b,h,w 0001-000 000070 h scr06 [r/w,w] b,h,w 00000000 smr06 [r/w,w] b,h,w 00000000 ssr06 [r/w,r] b,h,w 00001000 rdr06/tdr06 [r/w] b,h,w 00000000 lin-uart 6 000074 h escr06 [r/w] b,h,w 00000x00 eccr06 [r/w,r,w] b,h,w -00000xx fsr06 [r] b,h,w ---00000 fcr06 [r/w] b,h,w 0001-000 000078 h to 00007c h reserved reserved 000080 h bgr100 [r/w] b,h,w 00000000 bgr000 [r/w] b,h,w 00000000 bgr101 [r/w] b,h,w 00000000 bgr001 [r/w] b,h,w 00000000 baud rate generator uart (lin) 0 to 6 000084 h bgr102 [r/w] b,h,w 00000000 bgr002 [r/w] b,h,w 00000000 bgr103 [r/w] b,h,w 00000000 bgr003 [r/w] b,h,w 00000000 000088 h bgr104 [r/w] b,h,w 00000000 bgr004 [r/w] b,h,w 00000000 bgr105 [r/w] b,h,w 00000000 bgr005 [r/w] b,h,w 00000000 mb91460 series 33 (continued) address register block 0123 00008c h bgr106 [r/w] b,h,w 00000000 bgr006 [r/w] b,h,w 00000000 reserved baud rate generator uart (lin) 0 to 6 000090 h to 0000cc h reserved reserved 0000d0 h ibcr0 [r/w] b,h 00000000 ibsr0 [r] b,h 00000000 itbah0 [r/w] b,h ------00 itbal0 [r/w] b,h 00000000 i 2 c 0 0000d4 h itmkh0 [r/w] b,h 00----11 itmkl0 [r/w] b,h 11111111 ismk0 [r/w] b,h 01111111 isba0 [r/w] b,h -0000000 0000d8 h reserved idar0 [r/w] b,h 00000000 iccr0 [r/w] b -0011111 reserved 0000dc h ibcr1 [r/w] b,h 00000000 ibsr1 [r] b,h 00000000 itbah1 [r/w] b,h ------00 itbal1 [r/w] b,h 00000000 i 2 c 1 0000e0 h itmkh1 [r/w] b,h 00----11 itmkl1 [r/w] b,h 11111111 ismk1 [r/w] b,h 01111111 isba1 [r/w] b,h -0000000 0000e4 h reserved idar1 [r/w] b,h 00000000 iccr1 [r/w] b -0011111 reserved 0000e8 h to 0000fc h reserved reserved 000100 h gcn10 [r/w] b,h 00110010 00010000 reserved gcn20 [r/w] b ----0000 ppg control 0 to 3 000104 h gcn11 [r/w] b,h 00110010 00010000 reserved gcn21 [r/w] b ----0000 ppg control 4 to 7 000108 h reserved reserved 000110 h ptmr00 [r] h 11111111 11111111 pcsr00 [w] h xxxxxxxx xxxxxxxx ppg 0 000114 h pdut00 [w] h xxxxxxxx xxxxxxxx pcnh00 [r/w] b,h 00000000 pcnl00 [r/w] b,h 000000-0 000118 h ptmr01 [r] h 11111111 11111111 pcsr01 [w] h xxxxxxxx xxxxxxxx ppg 1 00011c h pdut01 [w] h xxxxxxxx xxxxxxxx pcnh01 [r/w] b,h 00000000 pcnl01 [r/w] b,h 000000-0 000120 h ptmr02 [r] h 11111111 11111111 pcsr02 [w] h xxxxxxxx xxxxxxxx ppg 2 000124 h pdut02 [w] h xxxxxxxx xxxxxxxx pcnh02 [r/w] b,h 00000000 pcnl02 [r/w] b,h 000000-0 mb91460 series 34 (continued) address register block 0123 000128 h ptmr03 [r] h 11111111 11111111 pcsr03 [w] h xxxxxxxx xxxxxxxx ppg 3 00012c h pdut03 [w] h xxxxxxxx xxxxxxxx pcnh03 [r/w] b,h 00000000 pcnl03 [r/w] b,h 000000-0 000130 h ptmr04 [r] h 11111111 11111111 pcsr04 [w] h xxxxxxxx xxxxxxxx ppg 4 000134 h pdut04 [w] h xxxxxxxx xxxxxxxx pcnh04 [r/w] b,h 00000000 pcnl04 [r/w] b,h 000000-0 000138 h ptmr05 [r] h 11111111 11111111 pcsr05 [w] h xxxxxxxx xxxxxxxx ppg 5 00013c h pdut05 [w] h xxxxxxxx xxxxxxxx pcnh05 [r/w] b,h 00000000 pcnl05 [r/w] b,h 000000-0 000140 h ptmr06 [r] h 11111111 11111111 pcsr06 [w] h xxxxxxxx xxxxxxxx pgg 6 000144 h pdut06 [w] h xxxxxxxx xxxxxxxx pcnh06 [r/w] b,h 00000000 pcnl06 [r/w] b,h 000000-0 000148 h ptmr07 [r] h 11111111 11111111 pcsr07 [w] h xxxxxxxx xxxxxxxx ppg 7 00014c h pdut07 [w] h xxxxxxxx xxxxxxxx pcnh07 [r/w] b,h 00000000 pcnl07 [r/w] b,h 000000-0 000170 h to 00017c h reserved reserved 000180 h reserved ics01 [r/w] b 00000000 reserved ics23 [r/w] b 00000000 input capture 0 to 3 000184 h ipcp0 [r] h xxxxxxxx xxxxxxxx ipcp1 [r] h xxxxxxxx xxxxxxxx 000188 h ipcp2 [r] h xxxxxxxx xxxxxxxx ipcp3 [r] h xxxxxxxx xxxxxxxx 00018c h ocs01 [r/w] 11101100 00001100 ocs23 [r/w] 11101100 00001100 output compare 0 to 3 000190 h occp0 [r/w] h xxxxxxxx xxxxxxxx occp1 [r/w] h xxxxxxxx xxxxxxxx 000194 h occp2 [r/w] h xxxxxxxx xxxxxxxx occp3 [r/w] h xxxxxxxx xxxxxxxx mb91460 series 35 (continued) address register block 0123 000198 h to 00019c h reserved reserved 0001a0 h aderh [r/w] b,h,w 00000000 00000000 aderl [r/w] b,h,w 00000000 00000000 a/d converter 0001a4 h adcs1 [r/w] b,h 00000000 adcs0 [r/w] b,h 00000000 adcr1 [r] b,h 000000xx adcr0 [r] b,h xxxxxxxx 0001a8 h adct1 [r/w] b,h 00010000 adct0 [r/w] b,h 00101100 adsch [r/w] b,h ---00000 adech [r/w] b,h ---00000 0001ac h reserved reserved 0001b0 h tmrlr0 [w] h xxxxxxxx xxxxxxxx tmr0 [r] h xxxxxxxx xxxxxxxx reload timer 0 (ppg 0, 1) 0001b4 h reserved tmcsrc0 [r/w] b,h ---00000 tmcsrc0 [r/w] b,h 0-000000 0001b8 h tmrlr1 [w] h xxxxxxxx xxxxxxxx tmr1 [r] h xxxxxxxx xxxxxxxx reload timer 1 (ppg 2, 3) 0001bc h reserved tmcsrc1 [r/w] b,h ---00000 tmcsrc1 [r/w] b,h 0-000000 0001c0 h tmrlr2 [w] h xxxxxxxx xxxxxxxx tmr2 [r] h xxxxxxxx xxxxxxxx reload timer 2 (ppg 4, 5) 0001c4 h reserved tmcsrc2 [r/w] b,h ---00000 tmcsrc2 [r/w] b,h 0-000000 0001c8 h tmrlr3 [w] h xxxxxxxx xxxxxxxx tmr3 [r] h xxxxxxxx xxxxxxxx reload timer 3 (ppg 6, 7) 0001cc h reserved tmcsrc3 [r/w] b,h ---00000 tmcsrc3 [r/w] b,h 0-000000 0001d0 h to 0001e4 h reserved reserved 0001e8 h tmrlr7 [w] h xxxxxxxx xxxxxxxx tmr7 [r] h xxxxxxxx xxxxxxxx reload timer 7 (a/d converter) 0001ec h reserved tmcsrc7 [r/w] b,h ---00000 tmcsrc7 [r/w] b,h 0-000000 0001f0 h tcdt0 [r/w] h xxxxxxxx xxxxxxxx reserved tccs0 [r/w] -0000000 free-run timer 0 (icu 0, 1) mb91460 series 36 (continued) address register block 0123 0001f4 h tcdt1 [r/w] h xxxxxxxx xxxxxxxx reserved tccs1 [r/w] -0000000 free-run timer 1 (icu 2, 3) 0001f8 h tcdt2 [r/w] h xxxxxxxx xxxxxxxx reserved tccs2 [r/w] -0000000 free-run timer 2 (ocu 0, 1) 0001fc h tcdt3 [r/w] h xxxxxxxx xxxxxxxx reserved tccs3 [r/w] -0000000 free-run timer 3 (ocu 2, 3) 000200 h dmaca0 [r/w] b,h,w* 1 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000204 h dmacb0 [r/w] b,h,w 00000000 00000000 xxxxxxxx xxxxxxxx 000208 h dmaca1 [r/w] b,h,w* 1 00000000 0000xxxx xxxxxxxx xxxxxxxx 00020c h dmacb1 [r/w] b,h,w 00000000 00000000 xxxxxxxx xxxxxxxx 000210 h dmaca2 [r/w] b,h,w* 1 00000000 0000xxxx xxxxxxxx xxxxxxxx 000214 h dmacb2 [r/w] b,h,w 00000000 00000000 xxxxxxxx xxxxxxxx 000218 h dmaca3 [r/w] b,h,w* 1 00000000 0000xxxx xxxxxxxx xxxxxxxx 00021c h dmacb3 [r/w] b,h,w 00000000 00000000 xxxxxxxx xxxxxxxx 000220 h dmaca4 [r/w] b,h,w* 1 00000000 0000xxxx xxxxxxxx xxxxxxxx 000224 h dmacb4 [r/w] b,h,w 00000000 00000000 xxxxxxxx xxxxxxxx 000228 h to 00023c h reserved 000240 h dmacr [r/w] b,h,w 00--0000 reserved 000244 h to 000254 h reserved reserved 000258 h to 000364 h reserved mb91460 series 37 (continued) address register block 0123 000368 h ibcr2 [r/w] b,h 00000000 ibsr2 [r] b,h 00000000 itbah2 [r/w] b,h ------00 itbal2 [r/w] b,h 00000000 i 2 c 2 00036c h itmkh2 [r/w] b,h 00----11 itmkl2 [r/w] b,h 11111111 ismk2 [r/w] b,h 01111111 isba2 [r/w] b,h -0000000 000370 h reserved idar2 [r/w] b,h 00000000 iccr2 [r/w] b -0011111 reserved 000374 h to 0003bc h reserved reserved 0003c0 h reserved 0003c4 h reserved isize [r/w] b ------11 instruction cache 0003d0 h reserved reserved 0003e4 h reserved ichrc [r/w] b 0-000000 instruction cache 0003e8 h to 0003ec h reserved reserved 0003f0 h bsd0 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h to 00043c h reserved reserved 000440 h icr00 [r/w] b,h,w ---11111 icr01 [r/w] b,h,w ---11111 icr02 [r/w] b,h,w ---11111 icr03 [r/w] b,h,w ---11111 interrupt controller 000444 h icr04 [r/w] b,h,w ---11111 icr05 [r/w] b,h,w ---11111 icr06 [r/w] b,h,w ---11111 icr07 [r/w] b,h,w ---11111 000448 h icr08 [r/w] b,h,w ---11111 icr09 [r/w] b,h,w ---11111 reserved icr11 [r/w] b,h,w ---11111 00044c h icr12 [r/w] b,h,w ---11111 icr13 [r/w] b,h,w ---11111 reserved mb91460 series 38 (continued) address register block 0123 000450 h icr16 [r/w] b,h,w ---11111 reserved icr19 [r/w] b,h,w ---11111 interrupt controller 000454 h icr20 [r/w] b,h,w ---11111 icr21 [r/w] b,h,w ---11111 icr22 [r/w] b,h,w ---11111 icr23 [r/w] b,h,w ---11111 000458 h reserved icr25 [r/w] b,h,w ---11111 icr26 [r/w] b,h,w ---11111 icr27 [r/w] b,h,w ---11111 00045c h reserved icr29 [r/w] b,h,w ---11111 reserved 000460 h reserved 000464 h reserved icr38 [r/w] b,h,w ---11111 icr39 [r/w] b,h,w ---11111 000468 h reserved icr42 [r/w] b,h,w ---11111 icr43 [r/w] b,h,w ---11111 00046c h reserved 000470 h icr48 [r/w] b,h,w ---11111 icr49 [r/w] b,h,w ---11111 icr50 [r/w] b,h,w ---11111 icr51 [r/w] b,h,w ---11111 000474 h reserved 000478 h reserved icr58 [r/w] b,h,w ---11111 icr59 [r/w] b,h,w ---11111 00047c h reserved icr62 [r/w] b,h,w ---11111 icr63 [r/w] b,h,w ---11111 000480 h rsrr [r/w] b,h,w 10000000 stcr [r/w] b,h,w 00110011 tbcr [r/w] b,h,w x0000x00 ctbr [w] b,h,w xxxxxxxx clock control 000484 h clkr [r/w] b,h,w 00000000 wpr [w] b,h,w xxxxxxxx divr0 [r/w] b,h,w 00000011 divr1 [r/w] b,h,w 00000000 000488 h reserved reserved mb91460 series 39 (continued) address register block 0123 00048c h plldivm [r/w] b,h ---00000 plldivn [r/w] b,h ---00000 reserved pll interface 000490 h reserved reserved 000494 h to 00049c h reserved 0004a0 h reserved wtcer [r/w] b,h ------00 wtcr [r/w] b,h 00000000 000-00-0 real-time clock 0004a4 h reserved wtbr [r/w] b, b,h ---xxxxx xxxxxxxx xxxxxxxx 0004a8 h wthr [r/w] b,h ---xxxxx wtmr [r/w] b,h --xxxxxx wtsr [r/w] b --xxxxxx reserved 0004ac h to 0004bc h reserved reserved 0004c0 h canpre [r/w] b,h 00000000 reserved can (clock control) 0004c4 h reserved hwdcs [r/w,w] b 00011000 hardware watchdog 0004c8 h oscr [r/w] b,h 00---000 reserved interval timer 0004cc h reserved reserved 0004d0 h reserved 0004d4 h shde [r/w] b 0------- reserved exte [r/w] b,h 00000000 extf [r/w] b,h 00000000 shutdown controller 0004d8 h extlv [r/w] b,h 00000000 00000000 reserved 0004dc h to 00063c h reserved reserved 000640 h asr0 [r/w] b,h,w 00000000 00000000 acr0* 2 [r/w] b,h,w 1111xx00 00000000 external bus 000644 h asr1 [r/w] b,h,w xxxxxxxx xxxxxxxx acr1 [r/w] b,h,w xxxxxxxx xxxxxxxx 000648 h asr2 [r/w] b,h,w xxxxxxxx xxxxxxxx acr2 [r/w] b,h,w xxxxxxxx xxxxxxxx 00064c h asr3 [r/w] b,h,w xxxxxxxx xxxxxxxx acr3 [r/w] b,h,w xxxxxxxx xxxxxxxx mb91460 series 40 (continued) address register block 0123 000650 h asr4 [r/w] b,h,w xxxxxxxx xxxxxxxx acr4 [r/w] b,h,w xxxxxxxx xxxxxxxx external bus 000654 h reserved 000658 h reserved 00065c h reserved 000660 h awr0 [r/w] b,h,w 01111111 11111011 awr1 [r/w] b,h,w xxxxxxxx xxxxxxxx 000664 h awr2 [r/w] b,h,w xxxxxxxx xxxxxxxx awr3 [r/w] b,h,w xxxxxxxx xxxxxxxx 000668 h awr4 [r/w] b,h,w xxxxxxxx xxxxxxxx reserved 00066c h reserved 000670 h reserved 000674 h reserved 000678 h iowr0 [r/w] b,h,w xxxxxxxx iowr1 [r/w] b,h,w xxxxxxxx iowr2 [r/w] b,h,w xxxxxxxx reserved 00067c h reserved 000680 h cser [r/w] b,h,w 00000001 cher [r/w] b,h,w 11111111 reserved tcr [r/w]* 3 b,h,w 0000xxxx 000684 h reserved 000688 h to 0007f8 h reserved 0007fc h reserved modr [w] b xxxxxxxx reserved mode register 000800 h to 000cfc h reserved reserved 000d00 h reserved r-bus port data direct read register 000d04 h reserved 000d08 h reserved 000d0c h reserved pdrd14 [r] b,h ----xxxx pdrd15 [r] b,h ----xxxx 000d10 h pdrd16 [r] b,h x------- pdrd17 [r] b,h xxxxxxxx pdrd18 [r] b,h -----xxx pdrd19 [r] b,h -xxx-xxx mb91460 series 41 (continued) address register block 0123 000d14 h pdrd20 [r] b,h -xxx-xxx pdrd21 [r] b,h -xxx-xxx pdrd22 [r] b,h xxxxxx-x pdrd23 [r] b,h -x-xxxxx r-bus port data direct read register 000d18 h pdrd24 [r] b,h xxxxxxxx reserved 000d1c h pdrd28 [r] b,h ---xxxxx pdrd29 [r] b,h xxxxxxxx reserved 000d20 h reserved 000d24 h to 000d3c h reserved reserved 000d40 h reserved r-bus port direction register 000d44 h reserved 000d48 h reserved 000d4c h reserved ddr14 [r/w] b,h ----0000 ddr15 [r/w] b,h ----0000 000d50 h ddr16 [r/w] b,h 0------- ddr17 [r/w] b,h 00000000 ddr18 [r/w] b,h -----000 ddr19 [r/w] b,h -000-000 000d54 h ddr20 [r/w] b,h -000-000 ddr21 [r/w] b,h -000-000 ddr22 [r/w] b,h 000000-0 ddr23 [r/w] b,h -0-00000 000d58 h ddr24 [r/w] b,h ---00000 reserved 000d5c h ddr28 [r/w] b,h ---00000 ddr29 [r/w] b,h 00000000 reserved 000d60 h reserved 000d64 h to 000d7c h reserved reserved 000d80 h reserved r-bus port function register 000d84 h reserved 000d88 h reserved 000d8c h reserved pfr14 [r/w] b,h ----0000 pfr15 [r/w] b,h ----0000 000d90 h pfr16 [r/w] b,h 0------- pfr17 [r/w] b,h 00000000 pfr18 [r/w] b,h -----000 pfr19 [r/w] b,h -000-000 mb91460 series 42 (continued) address register block 0123 000d94 h pfr20 [r/w] b,h -000-000 pfr21 [r/w] b,h -000-000 pfr22 [r/w] b,h 000000-0 pfr23 [r/w] b,h -0-00000 r-bus port function register 000d98 h pfr24 [r/w] b,h 00000000 reserved reserved reserved 000d9c h pfr28 [r/w] b,h ---00000 pfr29 [r/w] b,h 00000000 reserved reserved 000da0 h reserved 000da4 h to 000dbc h reserved reserved 000dc0 h reserved r-bus expansion port function register 000dc4 h reserved 000dc8 h reserved 000dcc h reserved epfr14 [r/w] b,h ----0000 epfr15 [r/w] b,h ----0000 000dd0 h epfr16 [r/w] b,h 0------- epfr17 [r/w] b,h 00000000 epfr18 [r/w] b,h -----000 epfr19 [r/w] b,h -000-000 000dd4 h epfr20 [r/w] b,h -000-000 epfr21 [r/w] b,h -000-000 epfr22 [r/w] b,h 000000-0 epfr23 [r/w] b,h -0-00000 000dd8 h epfr24 [r/w] b,h 00000000 reserved 000ddc h epfr28 [r/w] b,h ---00000 epfr29 [r/w] b,h 00000000 reserved 000de0 h reserved 000de4 h to 000dfc h reserved reserved 000e00 h to 000e3c h reserved mb91460 series 43 (continued) address register block 0123 000e40 h reserved r-bus pin input level selection register 000e44 h reserved 000e48 h reserved 000e4c h reserved pilr14 [r/w] b,h ----0000 pilr15 [r/w] b,h ----0000 000e50 h pilr16 [r/w] b,h 0------- pilr17 [r/w] b,h 00000000 pilr18 [r/w] b,h -----000 pilr19 [r/w] b,h -000-000 000e54 h pilr20 [r/w] b,h -000-000 pilr21 [r/w] b,h -000-000 pilr22 [r/w] b,h 000000-0 pilr23 [r/w] b,h -0-00000 000e58 h pilr24 [r/w] b,h 00000000 reserved 000e5c h pilr28 [r/w] b,h ---00000 pilr29 [r/w] b,h 00000000 reserved 000e60 h to 000ebc h reserved 000ec0 h reserved r-bus port pull-up/pull-down enable register 000ec4 h reserved 000ec8 h reserved 000ecc h reserved pper14 [r/w] b,h ----0000 pper15 [r/w] b,h ----0000 000ed0 h pper16 [r/w] b,h 0------- pper17 [r/w] b,h 00000000 pper18 [r/w] b,h -----000 pper19 [r/w] b,h -000-000 000ed4 h pper20 [r/w] b,h -000-000 pper21 [r/w] b,h -000-000 pper22 [r/w] b,h 000000-0 pper23 [r/w] b,h -0-00000 000ed8 h pper24 [r/w] b,h 00000000 reserved 000edc h pper28 [r/w] b,h ---00000 pper29 [r/w] b,h 00000000 reserved 000ee0 h reserved mb91460 series 44 (continued) address register block 0123 000ee4 h to 000efc h reserved reserved 000f00 h reserved r-bus port pull-up/pull-down control register 000f04 h reserved 000f08 h reserved 000f0c h reserved ppcr14 [r/w] b,h ----1111 ppcr15 [r/w] b,h ----1111 000f10 h ppcr16 [r/w] b,h 1------- ppcr17 [r/w] b,h -111-111 ppcr18 [r/w] b,h 111111-1 ppcr19 [r/w] b,h -1-11111 000f14 h ppcr20 [r/w] b,h -111-111 ppcr21 [r/w] b,h -111-111 ppcr22 [r/w] b,h 111111-1 ppcr23 [r/w] b,h -1-11111 000f18 h ppcr24 [r/w] b,h ---11111 reserved 000f1c h ppcr28 [r/w] b,h ---11111 ppcr29 [r/w] b,h 11111111 reserved 000f20 h reserved 000f24 h to 000f3c h reserved reserved 001000 h dmasa0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dmac 001004 h dmada0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001008 h dmasa1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00100c h dmada1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001010 h dmasa2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001014 h dmada2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx mb91460 series 45 (continued) address register block 0123 001018 h dmasa3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dmac 00101c h dmada3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001020 h dmasa4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001024 h dmada4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001028 h to 007ffc h reserved reserved 008000 h to 00bffc h reserved 00c000 h ctrlr0 [r/w] b,h 00000000 00000001 statr0 [r/w] b,h 00000000 00000000 can 0 control register 00c004 h errcnt0 [r] b,h,w 00000000 00000000 btr0 [r/w] b,h,w 00100011 00000001 00c008 h intr0 [r]b,h,w 00000000 00000000 testr0 [r/w]b,h,w 00000000 x0000000 00c00c h brpe0 [r/w]b,h,w 00000000 00000000 reserved 00c010 h if1creq0 [r/w] b,h 00000000 00000001 if1cmsk0 [r/w] b,h 00000000 00000000 can 0 if 1 register 00c014 h if1msk20 [r/w] b,h,w 11111111 11111111 if1msk10 [r/w] b,h,w 11111111 11111111 00c018 h if1arb20 [r/w] b,h,w 00000000 00000000 if1arb10 [r/w] b,h,w 00000000 00000000 00c01c h if1mctr0 [r/w] b,h,w 00000000 00000000 reserved 00c020 h if1dta10 [r/w] b,h,w 00000000 00000000 if1dta20 [r/w] b,h,w 00000000 00000000 00c024 h if1dtb10 [r/w] b,h,w 00000000 00000000 if1dtb20 [r/w]b,h,w 00000000 00000000 00c028 h to 00c02c h reserved 00c030 h if1dta20 [r/w] b,h,w 00000000 00000000 if1dta10 [r/w] b,h,w 00000000 00000000 00c034 h if1dtb20 [r/w] b,h,w 00000000 00000000 if1dtb10 [r/w] b,h,w 00000000 00000000 mb91460 series 46 (continued) address register block 0123 00c038 h to 00c03c h reserved can 0 if 1 register 00c040 h if2creq0 [r/w] b,h 00000000 00000001 if2cmsk0 [r/w] b,h 00000000 00000000 can 0 if 2 register 00c044 h if2msk20 [r/w] b,h,w 11111111 11111111 if2msk10 [r/w] b,h,w 11111111 11111111 00c048 h if2arb20 [r/w] b,h,w 00000000 00000000 if2arb10 [r/w] b,h,w 00000000 00000000 00c04c h if2mctr0 [r/w] b,h,w 00000000 00000000 reserved 00c050 h if2dta10 [r/w] b,h,w 00000000 00000000 if2dta20 [r/w] b,h,w 00000000 00000000 00c054 h if2dtb10 [r/w] b,h,w 00000000 00000000 if2dtb20 [r/w] b,h,w 00000000 00000000 00c058 h to 00c05c h reserved 00c060 h if2dta20 [r/w] b,h,w 00000000 00000000 if2dta10 [r/w] b,h,w 00000000 00000000 00c064 h if2dtb20 [r/w] b,h,w 00000000 00000000 if2dtb10 [r/w] b,h,w 00000000 00000000 00c068 h to 00c07c h reserved 00c080 h treqr20 [r] b,h,w 00000000 00000000 treqr10 [r] b,h,w 00000000 00000000 can 0 status flag 00c084 h reserved 00c088 h reserved 00c08c h reserved 00c090 h newdt20 [r] b,h,w 00000000 00000000 newdt10 [r] b,h,w 00000000 00000000 00c094 h reserved 00c098 h reserved 00c09c h reserved mb91460 series 47 (continued) address register block 0123 00c0a0 h intpnd20 [r] b,h,w 00000000 00000000 intpnd10 [r] b,h,w 00000000 00000000 can 0 status flag 00c0a4 h reserved 00c0a8 h reserved 00c0ac h reserved 00c0b0 h msgval20 [r] b,h,w 00000000 00000000 msgval10 [r] b,h,w 00000000 00000000 00c0b4 h reserved 00c0b8 h reserved 00c0bc h reserved 00c0c0 h to 00c0fc h reserved 00c100 h ctrlr1 [r/w] b,h 00000000 00000001 statr1 [r/w] b,h 00000000 00000000 can 1 control register 00c104 h errcnt1 [r] b,h,w 00000000 00000000 btr1 [r/w] b,h,w 00100011 00000001 00c108 h intr1 [r] b,h,w 00000000 00000000 testr1 [r/w] b,h,w 00000000 x0000000 00c10c h brpe1 [r/w] b,h,w 00000000 00000000 reserved 00c110 h if1creq1 [r/w] b,h 00000000 00000001 if1cmsk1 [r/w] b,h 00000000 00000000 can 1 if 1 register 00c114 h if1msk21 [r/w] b,h,w 11111111 11111111 if1msk11 [r/w] b,h,w 11111111 11111111 00c118 h if1arb21 [r/w] b,h,w 00000000 00000000 if1arb11 [r/w] b,h,w 00000000 00000000 00c11c h if1mctr1 [r/w] b,h,w 00000000 00000000 reserved 00c120 h if1dta11 [r/w] b,h,w 00000000 00000000 if1dta21 [r/w] b,h,w 00000000 00000000 00c124 h if1dtb11 [r/w] b,h,w 00000000 00000000 if1dtb21 [r/w] b,h,w 00000000 00000000 mb91460 series 48 (continued) address register block 0123 00c128 h to 00c12c h reserved can 1 if 1 register 00c130 h if1dta21 [r/w] b,h,w 00000000 00000000 if1dta11 [r/w] b,h,w 00000000 00000000 00c134 h if1dtb21 [r/w] b,h,w 00000000 00000000 if1dtb11 [r/w] b,h,w 00000000 00000000 00c138 h to 00c13c h reserved 00c140 h if2creq1 [r/w]b,h 00000000 00000001 if2cmsk1 [r/w]b,h 00000000 00000000 can 1 if 2 register 00c144 h if2msk21 [r/w]b,h,w 11111111 11111111 if2msk11 [r/w]b,h,w 11111111 11111111 00c148 h if2arb21 [r/w]b,h,w 00000000 00000000 if2arb11 [r/w]b,h,w 00000000 00000000 00c14c h if2mctr1 [r/w]b,h,w 00000000 00000000 reserved 00c150 h if2dta11 [r/w]b,h,w 00000000 00000000 if2dta21 [r/w]b,h,w 00000000 00000000 00c154 h if2dtb11 [r/w]b,h,w 00000000 00000000 if2dtb21 [r/w]b,h,w 00000000 00000000 00c158 h to 00c15c h reserved 00c160 h if2dta21 [r/w]b,h,w 00000000 00000000 if2dta11 [r/w]b,h,w 00000000 00000000 00c164 h if2dtb21 [r/w]b,h,w 00000000 00000000 if2dtb11 [r/w]b,h,w 00000000 00000000 00c168 h to 00c17c h reserved 00c180 h treqr21 [r]b,h,w 00000000 00000000 treqr11 [r]b,h,w 00000000 00000000 can 1 status flag 00c184 h reserved 00c188 h reserved 00c18c h reserved mb91460 series 49 (continued) address register block 0123 00c190 h newdt21 [r]b,h,w 00000000 00000000 newdt11 [r]b,h,w 00000000 00000000 can 1 status flag 00c194 h reserved 00c198 h reserved 00c19c h reserved 00c1a0 h intpnd21 [r]b,h,w 00000000 00000000 intpnd11 [r]b,h,w 00000000 00000000 00c1a4 h reserved 00c1a8 h reserved 00c1ac h reserved 00c1b0 h msgval21 [r]b,h,w 00000000 00000000 msgval11 [r]b,h,w 00000000 00000000 00c1b4 h reserved 00c1b8 h reserved 00c1bc h reserved 00c1c0 h to 00c1fc h reserved 00f000 h to 00fffc h reserved reserved 010000 h to 013ffc h cache tag way 1 (010000 h to 0107fc h ) instruction cache 014000 h to 017ffc h cache tag way 2 (014000 h to 0147fc h ) 018000 h to 01bffc h cache ram way 1 (018000 h to 0187fc h ) 01c000 h to 01fffc h cache ram way 2 (01c000 h to 01c7fc h ) mb91460 series 50 (continued) *1 : the lower 16 bits (dtc15 to dtc0) of dm aca0 to dmaca4 cannot be accessed in bytes. *2 : acr0[11:10] depends on the mode vector fetch information on bus width. *3 : tcr[3:0] init value = 0000 , the value is kept after rst. address register block 0123 020000 h to 02fffc h reserved reserved 030000 h to 03fffc h i/d-ram: 64 kbytes (instruction access is 0 wait cycle, data access is 1 wait cycle) i/d-ram 64 kbytes 040000 h to 07fffc h external memory area (256 kbytes) external bus 080000 h to 0bfffc h external memory area (256 kbytes) 0c0000 h to 0ffff4 h external memory area (256 kbytes) 0ffff8 h fmv [r] reset vector/ mode vector 0ffffc h frv [r] 100000 h to 13fffc h external memory area (256 kbytes) external bus 140000 h to 17fffc h external memory area (256 kbytes) 180000 h to 1bfffc h external memory area (256 kbytes) 1c0000 h to 1ffffc h external memory area (256 kbytes) 200000 h to 2ffffc h external memory area (1 mbyte) 300000 h to 3ffffc h external memory area (1 mbyte) mb91460 series 51 interrupt source table (continued) interrupt source interrupt number interrupt level offset tbr default address resource number* 1 deci- mal hexa- decimal setting register register address reset 0 00 ?? 3fc h 000ffffc h 2 mode vector 1 01 ?? 3f8 h 000ffff8 h 3 system reserved 2 02 ?? 3f4 h 000ffff4 h ? system reserved 3 03 ?? 3f0 h 000ffff0 h ? system reserved 4 04 ?? 3ec h 000fffec h ? system reserved 5 05 ?? 3e8 h 000fffe8 h ? system reserved 6 06 ?? 3e4 h 000fffe4 h ? coprocessor absent trap 7 07 ?? 3e0 h 000fffe0 h ? coprocessor error trap 8 08 ?? 3dc h 000fffdc h ? inte instruction 9 09 ?? 3d8 h 000fffd8 h ? instruction break exception 10 0a ?? 3d4 h 000fffd4 h ? operand break trap 11 0b ?? 3d0 h 000fffd0 h ? step trace trap 12 0c ?? 3cc h 000fffcc h ? nmi request (tool) 13 0d ?? 3c8 h 000fffc8 h ? undefined instruction exception 14 0e ?? 3c4 h 000fffc4 h ? nmi request 15 0f 15 (f) fixed 15 (f) fixed 3c0 h 000fffc0 h ? external interrupt 0 16 10 icr00 440 h 3bc h 000fffbc h ? external interrupt 1 17 11 3b8 h 000fffb8 h ? external interrupt 2 18 12 icr01 441 h 3b4 h 000fffb4 h ? external interrupt 3 19 13 3b0 h 000fffb0 h ? external interrupt 4 20 14 icr02 442 h 3ac h 000fffac h ? external interrupt 5 21 15 3a8 h 000fffa8 h ? external interrupt 6 22 16 icr03 443 h 3a4 h 000fffa4 h ? external interrupt 7 23 17 3a0 h 000fffa0 h ? external interrupt 8 24 18 icr04 444 h 39c h 000fff9c h ? external interrupt 9 25 19 398 h 000fff98 h ? external interrupt 10 26 1a icr05 445 h 394 h 000fff94 h ? external interrupt 11 27 1b 390 h 000fff90 h ? external interrupt 12 28 1c icr06 446 h 38c h 000fff8c h ? external interrupt 13 29 1d 388 h 000fff88 h ? external interrupt 14 30 1e icr07 447 h 384 h 000fff84 h ? external interrupt 15 31 1f 380 h 000fff80 h ? mb91460 series 52 (continued) interrupt source interrupt number interrupt level offset tbr default address resource number* 1 deci- mal hexa- decimal setting register register address reload timer 0 32 20 icr08 448 h 37c h 000fff7c h 4 reload timer 1 33 21 378 h 000fff78 h 5 reload timer 2 34 22 icr09 449 h 374 h 000fff74 h ? reload timer 3 35 23 370 h 000fff70 h ? system reserved 36 24 icr10 44a h 36c h 000fff6c h ? system reserved 37 25 368 h 000fff68 h ? system reserved 38 26 icr11 44b h 364 h 000fff64 h ? reload timer 7 39 27 360 h 000fff60 h ? free-run timer 0 40 28 icr12 44c h 35c h 000fff5c h ? free-run timer 1 41 29 358 h 000fff58 h ? free-run timer 2 42 2a icr13 44d h 354 h 000fff54 h ? free-run timer 3 43 2b 350 h 000fff50 h ? system reserved 44 2c icr14 44e h 34c h 000fff4c h ? system reserved 45 2d 348 h 000fff48 h ? system reserved 46 2e icr15 44f h 344 h 000fff44 h ? system reserved 47 2f 340 h 000fff40 h ? can0 48 30 icr16 450 h 33c h 000fff3c h ? can1 49 31 338 h 000fff38 h ? system reserved 50 32 icr17 451 h 334 h 000fff34 h ? system reserved 51 33 330 h 000fff30 h ? system reserved 52 34 icr18 452 h 32c h 000fff2c h ? system reserved 53 35 328 h 000fff28 h ? lin-usart 0 rx 54 36 icr19 453 h 324 h 000fff24 h 6 lin-usart 0 tx 55 37 320 h 000fff20 h 7 lin-usart 1 rx 56 38 icr20 454 h 31c h 000fff1c h 8 lin-usart 1 tx 57 39 318 h 000fff18 h 9 lin-usart 2 rx 58 3a icr21 455 h 314 h 000fff14 h ? lin-usart 2 tx 59 3b 310 h 000fff10 h ? lin-usart 3 rx 60 3c icr22 456 h 30c h 000fff0c h ? lin-usart 3 tx 61 3d 308 h 000fff08 h ? system reserved 62 3e icr23* 3 457 h 304 h 000fff04 h ? delay interrupt 63 3f 300 h 000fff00 h ? mb91460 series 53 (continued) interrupt source interrupt number interrupt level offset tbr default address resource number* 1 deci- mal hexa- decimal setting register register address system reserved* 2 64 40 (icr24) 458 h 2fc h 000ffefc h ? system reserved* 2 65 41 2f8 h 000ffef8 h ? lin-usart 4 rx 66 42 icr25 459 h 2f4 h 000ffef4 h 10 lin-usart 4 tx 67 43 2f0 h 000ffef0 h 11 lin-usart 5 rx 68 44 icr26 45a h 2ec h 000ffeec h 12 lin-usart 5 tx 69 45 2e8 h 000ffee8 h 13 lin-usart 6 rx 70 46 icr27 45b h 2e4 h 000ffee4 h ? lin-usart 6 tx 71 47 2e0 h 000ffee0 h ? system reserved 72 48 icr28 45c h 2dc h 000ffedc h ? system reserved 73 49 2d8 h 000ffed8 h ? i 2 c_0/i 2 c_2 74 4a icr29 45d h 2d4 h 000ffed4 h ? i 2 c_1/i 2 c_3 75 4b 2d0 h 000ffed0 h ? system reserved 76 4c icr30 45e h 2cc h 000ffecc h ? system reserved 77 4d 2c8 h 000ffec8 h ? system reserved 78 4e icr31 45f h 2c4 h 000ffec4 h ? system reserved 79 4f 2c0 h 000ffec0 h ? system reserved 80 50 icr32 460 h 2bc h 000ffebc h ? system reserved 81 51 2b8 h 000ffeb8 h ? system reserved 82 52 icr33 461 h 2b4 h 000ffeb4 h ? system reserved 83 53 2b0 h 000ffeb0 h ? system reserved 84 54 icr34 462 h 2ac h 000ffeac h ? system reserved 85 55 2a8 h 000ffea8 h ? system reserved 86 56 icr35 463 h 2a4 h 000ffea4 h ? system reserved 87 57 2a0 h 000ffea0 h ? system reserved 88 58 icr36 464 h 29c h 000ffe9c h ? system reserved 89 59 298 h 000ffe98 h ? system reserved 90 5a icr37 465 h 294 h 000ffe94 h ? system reserved 91 5b 290 h 000ffe90 h ? input capture 0 92 5c icr38 466 h 28c h 000ffe8c h ? input capture 1 93 5d 288 h 000ffe88 h ? input capture 2 94 5e icr39 467 h 284 h 000ffe84 h ? input capture 3 95 5f 280 h 000ffe80 h ? mb91460 series 54 (continued) interrupt source interrupt number interrupt level offset tbr default address resource number* 1 deci- mal hexa- decimal setting register register address system reserved 96 60 icr40 468 h 27c h 000ffe7c h ? system reserved 97 61 278 h 000ffe78 h ? system reserved 98 62 icr41 469 h 274 h 000ffe74 h ? system reserved 99 63 270 h 000ffe70 h ? output compare 0 100 64 icr42 46a h 26c h 000ffe6c h ? output compare 1 101 65 268 h 000ffe68 h ? output compare 2 102 66 icr43 46b h 264 h 000ffe64 h ? output compare 3 103 67 260 h 000ffe60 h ? system reserved 104 68 icr44 46c h 25c h 000ffe5c h ? system reserved 105 69 258 h 000ffe58 h ? system reserved 106 6a icr45 46d h 254 h 000ffe54 h ? system reserved 107 6b 250 h 000ffe50 h ? system reserved 108 6c icr46 46e h 24c h 000ffe4c h ? system reserved 109 6d 248 h 000ffe48 h ? system reserved 110 6e icr47* 3 46f h 244 h 000ffe44 h ? system reserved 111 6f 240 h 000ffe40 h ? ppg0 112 70 icr48 470 h 23c h 000ffe3c h 15 ppg1 113 71 238 h 000ffe38 h ? ppg2 114 72 icr49 471 h 234 h 000ffe34 h ? ppg3 115 73 230 h 000ffe30 h ? ppg4 116 74 icr50 472 h 22c h 000ffe2c h ? ppg5 117 75 228 h 000ffe28 h ? ppg6 118 76 icr51 473 h 224 h 000ffe24 h ? ppg7 119 77 220 h 000ffe20 h ? system reserved 120 78 icr52 474 h 21c h 000ffe1c h ? system reserved 121 79 218 h 000ffe18 h ? system reserved 122 7a icr53 475 h 214 h 000ffe14 h ? system reserved 123 7b 210 h 000ffe10 h ? system reserved 124 7c icr54 476 h 20c h 000ffe0c h ? system reserved 125 7d 208 h 000ffe08 h ? system reserved 126 7e icr55 477 h 204 h 000ffe04 h ? system reserved 127 7f 200 h 000ffe00 h ? mb91460 series 55 (continued) *1 : the peripheral resources to which rn (resource number) is assigned are capable of being dma transfer activation sources. in addition, rn has a one-to- one correspondence with an is (input source) of the dmac channel control register a(dmaca0 to dmaca4), and the is (input source) can be obtained by representing rn in a binary number and adding ?1? to the head of it. *2 : used by realos *3 : icr23 and icr47 are interchangeabl e by setting realos bit (address 0c03 h iso[0]). interrupt source interrupt number interrupt level offset tbr default address resource number* 1 deci- mal hexa- decimal setting register register address system reserved 128 80 icr56 478 h 1fc h 000ffdfc h ? system reserved 129 81 1f8 h 000ffdf8 h ? system reserved 130 82 icr57 479 h 1f4 h 000ffdf4 h ? system reserved 131 83 1f0 h 000ffdf0 h ? real-time clock 132 84 icr58 47a h 1ec h 000ffdec h ? system reserved 133 85 1e8 h 000ffde8 h ? a/d converter 0 134 86 icr59 47b h 1e4 h 000ffde4 h 14 system reserved 135 87 1e0 h 000ffde0 h ? system reserved 136 88 icr60 47c h 1dc h 000ffddc h ? system reserved 137 89 1d8 h 000ffdd8 h ? system reserved 138 8a icr61 47d h 1d4 h 000ffdd4 h ? system reserved 139 8b 1d0 h 000ffdd0 h ? time base overflow 140 8c icr62 47e h 1cc h 000ffdcc h ? pll clock gear 141 8d 1c8 h 000ffdc8 h ? dma controller 142 8e icr63 47f h 1c4 h 000ffdc4 h ? main/sub oscillation stabilization wait 143 8f 1c0 h 000ffdc0 h ? system reserved 144 90 ?? 1bc h 000ffdbc h ? used by int instruction 145 : 255 91 : ff ?? 1b8 h : 000 h 000ffdb8 h : 000ffc00 h ? mb91460 series 56 electrical characteristics 1. absolute maximum rating *1 : the parameter is based on v ss = av ss = 0.0 v. *2 : do not let av cc 3 and avrh exceed v cc +0.3 [v], for example, when the power is turned on. also, do not let av cc 3 exceed v cc 3. *3 : maximum output current is defined as the value of the peak current flowing thro ugh any one of the corresponding pins. *4 : average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 100 ms period. *5 : total average output current is defined as the value of the avera ge current flowing through all of the corresponding pins for a 100 ms period. (continued) parameter symbol rating unit remarks min max power supply voltage 1* 1 v cc 3v ss ? 0.5 v ss + 4.0 v power supply voltage 2* 1 v cc 5v ss ? 0.5 v ss + 6.0 v analog power supply voltage* 1 av cc 3v ss ? 0.5 v ss + 4.0 v *2 analog power supply voltage* 1 avrh v ss ? 0.5 v ss + 4.0 v *2 input voltage 1* 1 v i1 v ss ? 0.3 v cc 3 + 0.3 v input voltage 2* 1 v i2 v ss ? 0.3 v cc 5 + 0.3 v analog pin input voltage* 1 v ia v ss ? 0.3 av cc 3 + 0.3 v output voltage 1* 1 v o1 v ss ? 0.3 v cc 3 + 0.3 v output voltage 2* 1 v o2 v ss ? 0.3 v cc 3 + 0.3 v maximum clamp current i clamp ? 2.0 + 2.0 ma *6 total maximum clamp current ? i clamp ?? 20 ma *6 ?l? level maximum output current i ol ? 10 ma *3 ?l? level average output current i olav ? 8ma*4 ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma *5 ?h? level maximum output current i ol ? ? 10 ma *3 ?h? level average output current i ohav ? ? 4ma*4 ?h? level total maximum output current i oh ? ? 50 ma ?h? level total average output current i ohav ? ? 20 ma *5 power consumption p d ? 1000 mw operation temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 125 c mb91460 series 57 (continued) *6 : ? corresponding pins: pin number 2, 3, 116, 117, 120 to 125, 134 to 145, 148 to 160, 163 to 175 ? use within recommended operating conditions. ? use at dc voltage (current). ? the +b signal is an input signal exceeding v cc voltage. the +b signal should al ways be applied by connecting a limiting resistor between the +b signal and the microcontroller. ? the value of the limiting resistor should be set so t hat the current input to the microcontroller pin does not exceed rated values at any time regardless of instant aneously or constantly when the +b signal is input. ? note that when the microcontroller drive current is lo w, such as in the low power consumption modes, the +b input potential can increase the potential at the v cc pin via a protective diode, possibly affecting other devices. ? note that if the +b signal is input when the microcontrol ler is off (not fixed at 0 v), since the power is supplied through the pin, the microcontroller may operate incompletely. ? note that if the +b signal is input at power-on, sinc e the power is supplied through the pin, the power supply voltage may become the voltage at wh ich a power-on reset does not work. ? do not leave +b input pin open. ? note that analog input/output pins cannot accept +b signal input. ? example of recommended circuit : warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuit + b input (0 v to 16 v) limiting resistor protective diode mb91460 series 58 2. recommended operating conditions (v ss = av ss = 0.0 v) warning: : the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc 54.5 ? 5.5 v v cc 33.0 ? 3.6 v av cc 33.0 ? 3.6 v smoothing capacitor c s ? 4.7 (accuracy within 50 % ) ? f use a ceramic capacitor or a capacitor having the similar frequency characteristic. for a smoothing capacitor of vcc pin, use one having a capacitance value greater than c s . operating temperature t a ? 40 ? + 85 c c s c s av ss v ss c_2 c_1 mb91460 series 59 3. dc characteristics (v cc 5 = 4.5 v to 5.5 v, v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?h? level input voltage v ih1 p14_0 to p14_3, p15_0 to p15_3, p16_7, p17_0 to p17_7, p18_0 to p18_2, p19_0 to p19_2, p19_4 to p19_6, p20_0 to p20_2, p20_4 to p20_6, p21_0 to p21_2, p21_4 to p21_6, p22_0, p22_2, p22_3, p23_0 to p23_4, p23_6, p24_0 to p24_3, p24_6, p24_7, p28_0 to p28_4, p29_0 to p29_7, nmi , break, md0 to md3 ? 0.8 v cc ? v cc + 0.3 v cmos hysteresis input* 1 v ih2 p14_0 to p14_3, p15_0 to p15_3, p16_7, p17_0 to p17_7, p18_0 to p18_2, p19_0 to p19_2, p19_4 to p19_6, p20_0 to p20_2, p20_4 to p20_6, p21_0 to p21_2, p21_4 to p21_6, p22_0, p22_2, p22_3, p23_0 to p23_4, p23_6, p24_0 to p24_3, p24_6, p24_7, p28_0 to p28_4, p29_0 to p29_7, d16 to d31, dreq0, rdy, brq, icd0 to icd3 ? 0.7 v cc ? v cc + 0.3 v cmos input* 1 v ih3 p22_4 to p22_7, p24_4, p24_5 ? 0.7 v cc ? v cc 5 + 0.3 v i 2 c input* 2 mb91460 series 60 (v cc 5 = 4.5 v to 5.5 v, v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?l? level input voltage v il1 p14_0 to p14_3, p15_0 to p15_3, p16_7, p17_0 to p17_7, p18_0 to p18_2, p19_0 to p19_2, p19_4 to p19_6, p20_0 to p20_2, p20_4 to p20_6, p21_0 to p21_2, p21_4 to p21_6, p22_0, p22_2, p22_3, p23_0 to p23_4, p23_6, p24_0 to p24_3, p24_6, p24_7, p28_0 to p28_4, p29_0 to p29_7, nmi , break, md0 to md3 ? v ss ? 0.3 ? 0.2 v cc v cmos hysteresis input* 1 v il2 p14_0 to p14_3, p15_0 to p15_3, p16_7, p17_0 to p17_7, p18_0 to p18_2, p19_0 to p19_2, p19_4 to p19_6, p20_0 to p20_2, p20_4 to p20_6, p21_0 to p21_2, p21_4 to p21_6, p22_0, p22_2, p22_3, p23_0 to p23_4, p23_6, p24_0 to p24_3, p24_6, p24_7, p28_0 to p28_4, p29_0 to p29_7, d16 to d31, dreq0, rdy, brq, icd0 to icd3 ? v ss ? 0.3 ? 0.3 v cc v cmos input* 1 v il3 p22_4 to p22_7, p24_4, p24_5 ? v ss ? 0.3 ? 0.3 v cc 3vi 2 c input* 2 mb91460 series 61 (v cc 5 = 4.5 v to 5.5 v, v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?h? level output voltage v oh1 p14_0 to p14_3, p15_0 to p15_3, p17_0 to p17_3, p18_0 to p18_2, p19_0 to p19_2, p19_4 to p19_6, p20_0 to p20_2, p20_4 to p20_6, p21_0 to p21_2, p21_4 to p21_6, p22_0, p22_2, p22_3, p23_0 to p23_4, p23_6, p24_0 to p24_3, p24_6, p24_7 v cc = 5.0 v, i oh = 4.0 ma/ v cc = 3.3 v, i oh = 2.0 ma v cc ? 0.5 ?? v 3.3 v, 5 v switch pin* 3 v oh2 p16_7, p17_4 to p17_7, p28_0 to p18_4, p29_0 to p19_7, d16 to d31, icd0 to icd3, a00 to a23, as , bgrnt , cs0 to cs4 , dack0, deop0, iclk, ics0 to ics2, iord , iowr , rd , sysclk, wdreset , wr0 , wr1 v cc 3 = 3.3 v, i oh = 4.0 ma v cc 3 ? 0.5 ?? v 3.3 v dedicated pin mb91460 series 62 (v cc 5 = 4.5 v to 5.5 v, v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?l? level output voltage v ol1 p14_0 to p14_3, p15_0 to p15_3, p17_0 to p17_3, p18_0 to p18_2, p19_0 to p19_2, p19_4 to p19_6, p20_0 to p20_2, p20_4 to p20_6, p21_0 to p21_2, p21_4 to p21_6, p22_0, p22_2, p22_3, p23_0 to p23_4, p23_6, p24_0 to p24_3, p24_6, p24_7 v cc = 5.0 v, i ol = 4.0 ma/ v cc = 3.3 v, i ol = 2.0 ma ?? 0.4 v 3.3 v, 5 v switch pin* 3 v ol2 p16_7, p17_4 to p17_7, p28_0 to p28_4, p29_0 to p29_7, d16 to d31, icd0 to icd3, a00 to a23, as , bgrnt , cs0 to cs4 , dack0, deop0, iclk, ics0 to ics2, iord , iowr , rd , sysclk, wdreset , wr0 , wr1 v cc 3 = 3.3 v, i ol = 4.0 ma ?? 0.4 v 3.3 v dedicated pin v ol3 p22_4 to p22_7, p24_4, p24_5 v cc 3 = 3.3 v, i ol = 3.0 ma ?? 0.4 v i 2 c output input leak current i il all input pins v cc = dv cc = av cc = 5.0 v, v ss < vi < v cc ? 5 ?+ 5 a pull-up resistance value p up init , pull-up pin ? 25 50 100 k ? pull-down resistance value p down init , pull-up pin ? 25 50 100 k ? mb91460 series 63 (continued) (v cc 5 = 4.5 v to 5.5 v, v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) *1 : for a pin which can select the i/o power supply between 3.3 v and 5 v, the value is based on the power supply voltage currently used. although 5 v input is possible for trst , the input becomes cmos hysteres is based on the input threshold value v cc 3. *2 : although 5 v input is possible for i 2 c pin, the input is made base d on the input threshold value v cc 3. *3 : for a pin which can select the i/o power supply between 3.3 v and 5 v, the drive capability changes depending on the power supply voltage. parameter symbol pin name condition value unit remarks min typ max power sup- ply current i cc 3 vcc3 cpu core : 80 mhz, external bus : 40 mhz (no-load) peripheral macro : 10 mhz can : 20 mhz ? 120 150 ma i cc 5 vcc5 ? 15 20 ma i cch vcc3 t a = + 85 c ? 13maat stop vcc3 t a = + 85 c ? 10 50 a at shutdown input capacitance c in except vcc3, vcc5, vss, avcc, avss, avrh f = 1 mhz ? 515pf mb91460 series 64 4. ac characteristics (1) clock timing (v cc 5 = 4.5 v to 5.5 v, v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) note : these values are assumed based on t he division setting of each clock set to 16. ? conditions for measuring the clock timing ratings parameter symbol pin name con- dition value unit remarks min typ max clock frequency f c x0 x1 ? 10 18.5 20 mhz clock cycle time t c x0 x1 50 54 100 ns internal operation clock frequency f cp ? ? 4.6 ? 80 mhz cpu f cpp 4.6 ? 20 mhz peripheral f cpt 4.6 ? 40 mhz external bus f can ?? 20 mhz clock after divided by can prescaler internal operation clock cycle time t cp ? 12.5 ? 217 ns cpu t cpp 50 ? 217 ns peripheral t cpt 26.7 ? 217 ns external bus t can 50 ?? ns clock after divided by can prescaler 0. 8 v cc 0.2 v cc p wh p wl t c c = 50 pf output pin mb91460 series 65 (2) clock output timing (v cc 5 = 4.5 v to 5.5 v, v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) * : t cyc is the frequency of 1 clock cycle. (3) reset input ratings (v cc 5 = 4.5 v to 5.5 v, v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit remarks min max cycle time t cyc sysclk ? t cpt ? ns * sysclk sysclk t chcl sysclk 12.5 108.5 ns sysclk sysclk t clch sysclk 12.5 108.5 ns parameter symbol pin name condition value unit min max init input time (at power-on, at return from shutdown mode) t intl init ? 8 ? ms init input time (other than the above) 20 ? s v oh v ol t chcl t clch v oh t cyc s y s clk 0.2 v cc t intl init mb91460 series 66 (4) normal bus access read/write operation (v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) * : when the bus timing is delayed by automatic wait insertion or rdy input, add the time (t cyc the number of cycles added for the delay) to this rating. parameter symbol pin name condition value unit remarks min max cs0 to cs4 setup t cslch sysclk cs0 to cs4 ? 3 ? ns t csdlch ? 3 ? ns cs0 to cs4 hold t chcsh 3t cyc /2 + 6ns address setup t asch sysclk a23 to a00 3 ? ns t aswl wr0 , wr1 a23 to a00 3 ? ns t asrl rd a23 to a00 3 ? ns address hold t chax sysclk a23 to a00 3t cyc /2 + 6ns t whax wr0 , wr1 a23 to a00 3 ? ns t rhax rd a23 to a00 3 ? ns valid address/valid data input time t avdv a23 to a00 d31 to d16 ? 3/2 t cyc ? 15 ns * wr0 , wr1 delay time t chwl sysclk wr0 , wr1 ? 6ns t chwh ? 6ns data setup time (wrn rising) t dswh d31 to d16 wr0 , wr1 t cyc ? 3 ? ns data hold time (wrn rising) t whdx d31 to d16 wr0 , wr1 3 ? ns wr0 , wr1 minimum pulse width t wlwh wr0 , wr1 t cyc ? 3 ? ns rd delay time t chrl sysclk rd ? 6ns t chrh ? 6ns data setup time (rd rising) t dsrh d31 to d16 rd 20 ? ns data hold time (rd rising) t rhdx d31 to d16 rd 0 ? ns rd minimum pulse width t rlrh rd t cyc ? 3 ? ns as setup t aslch sysclk as 3 ? ns as hold t chash 3t cyc /2 + 6ns mb91460 series 67 v oh v ol t cyc t a s lch s y s clk a s c s 0 to c s 4 a2 3 to a00 rd d 3 1 to d16 wr0, wr1 d 3 1 to d16 v oh v oh v oh v oh t cha s h ba1 v ol v ol v ol v ol v oh v oh v oh v oh t c s lch t a s ch t chc s h t chax t chrl t rlrh t chrh t rhax t a s rl t avdv t chwl t wlwh t chwh t whax t whdx t d s wh v ol v oh v ol v oh v ol v oh v il v ih v il v ih re a d t a s wl t d s rh t rhdx write mb91460 series 68 (5) ready input timing (v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit min max rdy setup time sysclk t rdys sysclk rdy ? 10 ? ns sysclk rdy hold time t rdyh sysclk rdy 0 ? ns v oh v ol t cyc t rdy s s y s clk v oh v ol v oh v ol v oh v ol t rdyh t rdy s t rdyh v oh v ol v oh v ol when rdy wait is applied when rdy wait is not applied mb91460 series 69 (6) hold timing (v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) note : after a brq is captured, a minimu m of 1 cycle is required before bgrnt changes. parameter symbol pin name condition value unit min max bgrnt delay time t chbgl sysclk bgrnt ? ? 10 ns t chbgh ? 10 ns bgrnt rising from pin floating t xhal ? t cyc ? 10 t cyc + 10 ns bgrnt rising from pin valid t hahv bgrnt t cyc ? 10 t cyc + 10 ns v oh t cyc s y s clk v oh v oh t xhal v oh t chbgl t hahv t chbgh v ol v oh bgrnt brq high impedance each pin mb91460 series 70 (7) lin-uart timing (v cc 5 = 4.5 v to 5.5 v, v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) notes : ? above values are ac characteri stics for clk synchronous mode. ? t cycp is the cycle time of the peripheral clock. parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck0 to sck6 internal shift clock mode 5t cycp ? ns sck sot delay time t slov sck0 to sck6, sot0 to sot6 ? 50 + 50 ns valid sin sck t ivsh sck0 to sck6, sin0 to sin6 t cycp + 80 ? ns sck valid sin hold time t shix sck0 to sck6, sin0 to sin6 0 ? ns serial clock ?h? pulse width t shsl sck0 to sck6 external shift clock mode t cycp + 10 ? ns serial clock ?l? pulse width t slsh sck0 to sck6 3t cycp ? ns sck sot delay time t slov sck0 to sck6, sot0 to sot6 ? 150 ns valid sin sck t ivsh sck0 to sck6, sin0 to sin6 30 ? ns sck valid sin hold time t shix sck0 to sck6, sin0 to sin6 t cycp + 30 ? ns sck rising time t f sck0 to sck6 ? 10 ns sck falling time t r sck0 to sck6 ? 10 ns mb91460 series 71 internal shift clock mode external shift clock mode t iv s h v oh t s hix t s lov t s cyc v ol s ot0 to s ot6 s ck0 to s ck6 v ol v ol v ol v ol v oh v oh v oh s in0 to s in6 t iv s h v oh t s hix t s lov t s l s h v ol s ot0 to s ot6 s ck0 to s ck6 v ol v ol v ol v ol v oh v oh v oh s in0 to s in6 t s h s l v ol mb91460 series 72 (8) dma controller timing (v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) note : after a breq is captured, a mini mum of 1 cycle is required before bgrnt changes. parameter symbol pin name condition value unit min max dreq0 input pulse t drwh dreq0 ? ? 10 ns dack0 delay time t cldl dack0 ? 10 ns t cldh ? 10 ns deop0 delay time t clel deop0 ? 10 ns t cleh ? 10 ns iord delay time t chirl iord ? 10 ns t chirh ? 10 ns iowr delay time t chiwl iowr ? 10 ns t chiwh ? 10 ns v ol t cyc v oh dack0 deop0 iord iowr dreq0 s y s clk v oh v oh v oh v oh v oh v oh v oh v oh v ol v ol v ol v ol t cldl t cldh t clel t cleh t chirl t chirh t chiwl t chiwh t drwh mb91460 series 73 (9) free-run timer clock (v cc 5 = 4.0 v to 5.5 v, v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) note : t cycp is the cycle time of the peripheral clock. (10) trigger input timing (v cc 5 = 4.0 v to 5.5 v, v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) note : t cycp is the cycle time of the peripheral clock. parameter symbol pin name condition value unit min max input pulse width t tiwh t tiwl frck0 to frck3 ? 4t cycp ? ns parameter symbol pin name condition value unit min max input capture input trigger t inp icu0 to icu3 ? 5t cycp ? ns a/d converter trigger t atgx atg ? 5t cycp ? ns t tiwh t tiwl frck0 to frck 3 icu0 to icu 3 , at g t atgx, t inp mb91460 series 74 5. a/d converter (1) electrical characteristics (v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = ? 40 c to + 85 c) *1 : measured in the cpu sleep state *2 : set the peripheral clock and conversion time setting r egister to set a time equal to or longer than this time. *3 : the current when a/d converter is not op erating, or in the cpu stop mode (at v cc 3 = av cc 3 = avrh = 3.3 v). parameter symbol pin name value unit remarks min typ max resolution ?? ?? 10 bit total error* 1 ?? ?? 3lsb at av cc 3 = 3.3 v, avrh = 3.3 v linearity error* 1 ?? ?? 2.5 lsb differential linearity error* 1 ?? ?? 1.9 lsb zero transition voltage* 1 v ot an0 to an12 avrl ? 1.5 avrl ? 0.5 avrl ? 2.5 lsb full transition voltage* 1 v fst an0 to an12 avrh ? 3.5 avrh ? 1.5 avrh ? 0.5 lsb conversion time ?? 1 * 2 ?? s analog port input current i ain an0 to an12 ?? 10 a analog input voltage v ain an0 to an12 av ss ? avrh v reference voltage ? avrh av ss ? av cc 3v analog power supply current (analog + digital) i a avcc3 ? 1.5 2.5 ma including reference supply i ah * 3 ?? 10 a analog input equivalent capacity cin an0 to an12 ?? 14.7 pf analog input equivalent resistance rin an0 to an12 ?? 1.9 k ? av cc 3 2.7 v output impedance of analog signal source rext ??? 1.9 k ? av cc 3 2.7 v mb91460 series 75 (2) cautions relating to the a/d converter the diagram below shows the equi valent circuit of the sampling circuit in the a/d converter. the output impedance of the external ci rcuit connected to the analog input must satisfy the following criteria. ? the recommended output impedance for the external circuit is 1.9 k ? or less. ? if an external capacitor is used, remember to consider the capacitive voltage divide r effect due to the external capacitor and the internal capacitor in the chip. accord ingly, an external capacitance several thousand times that of the internal capacitance is recommended. ? the analog voltage sampling period may be too short if the output impedance of the external circuit is high. in this case, select rext and tsamp such that they satisfy the following condition. rext = tsamp/ (7 cin) ? rin rext : output impedance of the analog signal source tsamp : sampling time cin : equivalent capacitance of analog input rin : equivalent resistance of analog input an a log s ign a l s o u rce rext an a log inp u t pin an a log s w rin:1.9 k ? (m a x) cin:14.7 pf (m a x) a/d converter device intern a l circ u it ? input impedance mb91460 series 76 (3) definition of a/d converter terms resolution analog variation that is recognizable by an a/d converter. linearity error deviation between actual conversion characteristics and a straight line connecting zero transition point (00 0000 0000 ? 00 0000 0001) and full scale transition point (11 1111 1110 ? 11 1111 1111). differential linearity error deviation of input voltage, which is required for ch anging output code by 1 lsb, from an ideal value. total error this error indicates the difference between actual and t heoretical values, including the zero transition error/ full scale transition error/linearity error. 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh 0.5 lsb' {1 lsb (n ? 1) + 0.5 lsb} 1.5 lsb analog input total error digital output actual conversion characteristics v nt (measurement value) ideal characteristics actual conversion characteristics total error of digital output n = 1 lsb' v nt ? {1 lsb' (n ? 1) + 0.5 lsb'} n : a/d converter digital output value v ot ' (ideal value) = av ss + 0.5 lsb' [v] v fst ' (ideal value) = av ? 1.5 lsb' [v] v nt : a voltage at which digital output transits from (n + 1) h to n h 1lsb' (ideal value) = 1024 avrh ? av ss [v] mb91460 series 77 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh {1 lsb (n ? 1) + v ot } (n+1) h n h (n-1) h (n-2) h av ss avrh analog input analog input differential linearity error linearity error digital output digital output actual conversion characteristics v fst (measure- ment value) v nt (measure- ment value) actual conversion characteristics ideal characteristics v to (measurement value) actual conversion characteristics v nt (measure- ment value) v fst (measure- ment value) linearity error of digital output n = 1lsb v nt ? {1lsb (n ? 1) + v ot } [lsb] differential linearity error of digital output n = 1lsb v ( n + 1 ) t ? v nt [lsb] 1lsb = 1022 v fst ? v ot [v] n : a/d converter digital output value v ot : a voltage at which digital output transits from 000 h to 001 h . v fst : a voltage at which digital output transits from 3fe h to 3ff h . actual conversion characteristics ideal characteristics mb91460 series 78 ordering information part number package remarks MB91461PMC-GSE1 176-pin, plastic lqfp (fpt-176p-m07) lead-free package mb91460 series 79 package dimension please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 176-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 24.0 24.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max code (reference) p-lqfp-0176-2424-0.50 176-pin pl as tic lqfp (fpt-176p-m07) (fpt-176p-m07) c 2004 fujit s u limited f17601 3s -c-1-1 det a il s of "a" p a rt 0?~ 8 ? 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.25(.010) ( s t a nd off) (.004.004) 0.100.10 1.50 +0.20 ? 0.10 +.00 8 ? .004 .059 (mo u nting height) 0.0 8 (.00 3 ) (.006.002) 0.1450.055 "a" index 1 lead no. 44 45 88 8 9 1 3 2 1 33 176 0.50(.020) 0.220.05 (.009.002) m 0.0 8 (.00 3 ) * 24.000.10(.945.004) s q 26.000.20(1.024.00 8 ) s q dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : v a l u e s do not incl u de re s in protr us ion. re s in protr us ion i s +0.25(.010)m a x(e a ch s ide). note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss note 3 )pin s width do not incl u de tie ba r c u tting rem a inder. mb91460 series f0704 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept. |
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